External access permission to the debug registers is subject
to the conditions at the time of the access. The following table describe the processor response to accesses
through the external debug interface.
Table 10-1 External register access conditions
||EDPRSR.PU is 0
Core power domain is completely off, or in a low-power state where the Core power
domain registers cannot be accessed.
Note If debug power is off then all external debug and memory-mapped
register accesses return an error.
||EDPRSR.DLK is 1
||OS Double Lock is locked.
||OSLSR_EL1.OSLK is 1
||OS Lock is locked.
|External debug access disabled. When an error is returned because
of the EDAD condition, and this is the highest priority error condition, EDPRSR.SDAD
is set to 1. Otherwise SDAD is unchanged.
||Memory-mapped interface only
||Software Lock is locked. For the external debug interface, ignore
||None of the conditions apply, normal access.
The following table shows an example
of external register access conditions for access to a Performance Monitors register.
To determine the access permission for the register, scan the columns
from left to right. Stop at the first column whose condition is
true, the entry gives the access permission of the register and
Table 10-2 External register access conditions example