ARM Cortex-A72 MPCore Processor Technical Reference Manual : 10.4.1 Debug Breakpoint Control Registers, EL1

10.4.1 Debug Breakpoint Control Registers, EL1

The DBGBCRn_EL1characteristics are:

Purpose

Holds control information for a breakpoint. Each DBGBVR_EL1 is associated with a DBGBCR_EL1 to form a Breakpoint Register Pair (BRP). DBGBVRn_EL1 is associated with DBGBCRn_EL1to form BRPn.

Note

The range of n for DBGBCRn_EL1 is 0 to 5.

Usage constraints

The accessibility to the DBGBCRn_EL1 by Exception level is:

EL0	EL1(NS)	EL1(S)	EL2	EL3(SCR.NS = 1)	EL3(SCR.NS = 0)
-	RW	RW	RW	RW	RW

The external debug accessibility to the DBGBCRn_EL1 by condition code is:

Off	DLK	OSLK	EDAD	SLK	Default
Error	Error	Error	Error	RO	RW

Table 11-1 External register access conditions describes the access conditions.

Configurations

The DBGBCRn_EL1 is Common to Secure and Non-secure states and architecturally mapped to:

The AArch32 DBGBCRn registers.
The external DBGBCRn_EL1 registers.

Attributes

See the register summary in Table 10-3 AArch64 debug register summary.

The debug logic reset value of a DBGBCRn_EL1 is UNKNOWN.

The following figure shows the DBGBCRn_EL1bit assignments.

Figure 10-2 DBGBCR

The following table shows the DBGBCRn_EL1 bit assignments.

Table 10-4 DBGBCRn_EL1 bit assignments

Bits Name Function

[31:24]

Reserved, RES0.

[23:20]

Breakpoint Type. This field controls the behavior of Breakpoint debug event generation. This includes the meaning of the value held in the associated DBGBVR, indicating whether it is an instruction address match or mismatch or a Context match. It also controls whether the breakpoint is linked to another breakpoint. The possible values are:

`0b0000`	Unlinked instruction address match.
`0b0001`	Linked instruction address match.
`0b0010`	Unlinked ContextIDR match.
`0b0011`	Linked ContextIDR match.
`0b0100`	Unlinked instruction address mismatch.
`0b0101`	Linked instruction address mismatch.
`0b1000`	Unlinked VMID match.
`0b1001`	Linked VMID match.
`0b1010`	Unlinked VMID + CONTEXTIDR match.
`0b1011`	Linked VMID + CONTEXTIDR match.

All other values are reserved.

The field break down is:

BT[0] Enable linking.

BT[3,1]

Base type. If the breakpoint is not context-aware, these bits are RES0. Otherwise, the possible values are:

`0b00`	Match address.
`0b01`	Match context ID.
`0b10`	Match VMID.
`0b11`	Match VMID and context ID.

BT[2] Mismatch. This bit is ignored in AArch64 state, and in EL0 if EL1 is using AArch64. If EL1 using AArch32 is not implemented, this bit is RES0. The address in DBGBVRn_EL1 is the address of an instruction to be stepped.

[19:16]

LBN

Linked breakpoint number. For Linked address matching breakpoints, this specifies the index of the Context-matching breakpoint linked to.

[15:14]

SSC

Security State Control. Determines the Security states that a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the AMC and PMC fields.

This field is used with the Higher Mode Control (HMC), and Privileged Mode Control (PMC), fields to determine the mode and Security states that can be tested.

See the ARM^® Architecture Reference Manual ARMv8 for possible values of the fields.

[13]

HMC

Hyp Mode Control bit. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This bit must be interpreted along with the SSC and PMC fields.

This bit is used with the SSC and PMC fields to determine the mode and Security states that can be tested.

See the ARM^® Architecture Reference Manual ARMv8 for possible values of the fields.

[12:9] - Reserved, RES0.

[8:5]

BAS^a

Byte Address Select. Defines which halfwords a regular breakpoint matches, regardless of the instruction set and Execution state. A debugger must program this field as follows:

`0x3`	Match the T32 instruction at DBGBVR`n`.
`0xC`	Match the T32 instruction at DBGBVR`n`+2.
`0xF`	Match the A64 or A32 instruction at DBGBVR`n`, or context match.

All other values are reserved.

Note

ARMv8 does not support direct execution of Java bytecodes. BAS[3] and BAS[1] ignore writes and on reads return the values of BAS[2] and BAS[0] respectively.

[4:3] - Reserved, RES0.

[2:1]

PMC

Privileged Mode Control. Determines the Exception level or levels that a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and AMC fields.

This field is used with the SSC and HMC fields to determine the mode and Security states that can be tested.

See the ARM^® Architecture Reference Manual ARMv8 for possible values of the fields.

Note

Bits[2:1] has no effect for accesses made in Hyp mode.

[0]

Enable breakpoint. This bit enables the BRP:

0	BRP disabled.
1	BRP enabled.

A BRP never generates a Breakpoint debug event when it is disabled.

Note

The value of DBGBCR.E is UNKNOWN on reset. A debugger must ensure that DBGBCR.E has a defined value before it programs DBGDSCR.MDBGen and DBGDSCR.HDBGen to enable debug.

To access the DBGBCRn_EL1 in AArch64 state, read or write the register with:

MRS <Xt>, DBGBCRn_EL1; Read Debug Breakpoint Control Register n
MSR DBGBCRn_EL1, <Xt>; Write Debug Breakpoint Control Register n

To access the DBGBCRn in AArch32 state, read or write the CP14 register with:

MRC p14, 0, <Rt>, c0, cn, 4; Read Debug Breakpoint Control Register n
MCR p14, 0, <Rt>, c0, cn, 4; Write Debug Breakpoint Control Register n

The DBGBCRn_EL1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x4n8.

^a See the ARM^® Architecture Reference Manual ARMv8 for more information on how the BAS field is interpreted by hardware.

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