10.5 AArch32 debug register summary

The following table summarizes the 32-bit and 64-bit debug control registers that are accessible in AArch32 state from the internal CP14 interface.

These registers are accessed by the MCR and MRC instructions in the order of CRn, op1, CRm, op2 or MCRR and MRRC instructions in the order of CRm, op1.
The table also shows the offset address for the AArch32 registers that are accessible from the internal memory-mapped interface and the external debug interface. See 10.7 Memory-mapped register summary for a complete list of registers accessible from the internal memory-mapped and the external debug interface.

Table 10-6 AArch32 debug register summary

Offset CRn op1 CRm op2 Name Type Width Description
- c0 0 c0 0 DBGDIDR RO 32-bit 10.6.1 Debug ID Register
-     2 DBGDTRRXext RW 32-bit Debug Data Transfer Register, Receive, External View 
0x400     4 DBGBVR0 RW 32-bit Debug Breakpoint Value Register 0 a
0x408     5 DBGBCR0 RW 32-bit 10.4.1 Debug Breakpoint Control Registers, EL1
0x800     6 DBGWVR0 RW 32-bit Debug Watchpoint Value Register 0 a
0x808     7 DBGWCR0 RW 32-bit 10.4.2 Debug Watchpoint Control Registers, EL1
-     c1 0 DBGDSCRint RO 32-bit Debug Status and Control Register, Internal View a
0x410     4 DBGBVR1 RW 32-bit Debug Breakpoint Value Register 1 a
0x418     5 DBGBCR1 RW 32-bit 10.4.1 Debug Breakpoint Control Registers, EL1
0x810     6 DBGWVR1 RW 32-bit Debug Watchpoint Value Register 1 a
0x818     7 DBGWCR1 RW 32-bit 10.4.2 Debug Watchpoint Control Registers, EL1
-     c2 0 DBGDCCINT RW 32-bit Debug Comms Channel Interrupt Enable Register a
-     2 DBGDSCRext RW 32-bit Debug Status and Control Register, External View a
0x420     4 DBGBVR2 RW 32-bit Debug Breakpoint Value Register 2 a
0x428     5 DBGBCR2 RW 32-bit 10.4.1 Debug Breakpoint Control Registers, EL1
0x820     6 DBGWVR2 RW 32-bit Debug Watchpoint Value Register 2 a
0x828     7 DBGWCR2 RW 32-bit 10.4.2 Debug Watchpoint Control Registers, EL1
-     c3 2 DBGDTRTXext RW 32-bit Debug Data Transfer Register, Transmit, External View a
0x430     4 DBGBVR3 RW 32-bit Debug Breakpoint Value Register 3 a
0x438     5 DBGBCR3 RW 32-bit 10.4.1 Debug Breakpoint Control Registers, EL1
0x830     6 DBGWVR3 RW 32-bit Debug Watchpoint Value Register 3 a
0x838     7 DBGWCR3 RW 32-bit 10.4.2 Debug Watchpoint Control Registers, EL1
0x440     c4 4 DBGBVR4 RW 32-bit Debug Breakpoint Value Register 4 a
0x448     5 DBGBCR4 RW 32-bit 10.4.1 Debug Breakpoint Control Registers, EL1
0x08C c0 0 c5 0 DBGDTRTXint WO 32-bit Debug Data Transfer Register, Transmit, Internal View a
        DBGDTRRXint RO 32-bit Debug Data Transfer Register, Receive, Internal View a
0x450     4 DBGBVR5 RW 32-bit Debug Breakpoint Value Register 5 a
0x458     5 DBGBCR5 RW 32-bit 10.4.1 Debug Breakpoint Control Registers, EL1
-     c6 0 DBGWFAR RW 32-bit Debug Watchpoint Fault Address Registerb, RES0.
0x098     2 DBGOSECCR RW 32-bit Debug OS Lock Exception Catch Control Register a
-     c7 0 DBGVCR RW 32-bit Debug Vector Catch Register a
- c1 0 c0 0 DBGDRAR[31:0] RO 32-bit Debug ROM Address Register a
- - 0 c1 - DBGDRAR[63:0] 64-bit
0x300 c1 0 c0 4 DBGOSLAR WO 32-bit Debug OS Lock Access Register a
-     c1 4 DBGOSLSR RO 32-bit Debug OS Lock Status Register a
-     c3 4 DBGOSDLR RW 32-bit Debug OS Double Lock Register a
0x444     c4 1 DBGBXVR4 RW 32-bit Debug Breakpoint Extended Value Register 4 a
0x310     4 DBGPRCR RW 32-bit Debug Power/Reset Control Register a
0x454     c5 1 DBGBXVR5 RW 32-bit Debug Breakpoint Extended Value Register 5 a
- c2 2 c0 0 DBGDSAR[31:0] RO 32-bit Debug Self Address Registerc RES0
- - 0 c2 - DBGDSAR[63:0]c 64-bit
- c7 0 c0 7 DBGDEVID2 RO 32-bit Debug Device ID Register 2, RES0
-     c1 7 DBGDEVID1 RO 32-bit 10.6.2 Debug Device ID Register 1
-     c2 7 DBGDEVID RO 32-bit 10.6.3  Debug Device ID Register
0xFA0     c8 6 DBGCLAIMSET RW 32-bit Debug Claim Tag Set Register a
0xFA4     c9 6 DBGCLAIMCLR RW 32-bit Debug Claim Tag Clear Register a
0xFB8     c14 6 DBGAUTHSTATUS RO 32-bit Debug Authentication Status Register a
a See the ARM® Architecture Reference Manual ARMv8 for more information.
b Previously returned information about the address of the instruction that accessed a watchpoint address. This register is now deprecated and is RES0.
c Previously defined the offset from the base address defined in DBGDRAR of the physical base address of the debug registers for the processor. This register is now deprecated and RES0.
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