10.8.4 External Debug Integration Input Status Register

The EDITISR characteristics are:
Purpose
Enables the values of signal inputs to be read when EDITCTRL.IME is set.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
Error Error Error - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
EDITISR is in the Core power domain.
Attributes
See 10.7 Memory-mapped register summary.
The following figure shows the EDITISR bit assignments.
Figure 10-10 EDITISR bit assignments
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The following table shows the EDITISR bit assignments.

Table 10-14 EDITISR bit assignments

Bits Name Function
[31:3] - Reserved, RES0.
[2] CTI DBGRESTART CTI debug restart bit. This bit reads the state of the debug restart input coming from the CTI into the debug unit.
[1] CTI EDBGRQ CTI debug request bit. This bit reads the state of the debug request input coming from the CTI into the debug unit.
[0] EDBGRQ This bit reads the state of the EDBGRQ input.
Related information
10.8.5 External Debug Integration Mode Control Register
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