10.10.1 Debug memory map

The memory map supports up to four cores in a cluster. The following table shows the address mapping for the debug trace components.

Table 10-29 Address mapping for debug trace components

Address range Component a
0x000000 - 0x00FFFF ROM table
0x010000 - 0x01FFFF Core 0 Debug
0x020000 - 0x02FFFF Core 0 CTI
0x030000 - 0x03FFFF Core 0 PMU
0x040000 - 0x04FFFF Core 0 Trace
0x050000 - 0x10FFFF Reserved
0x110000 - 0x11FFFF Core 1 Debug
0x120000 - 0x12FFFF Core 1 CTI
0x130000 - 0x13FFFF Core 1 PMU
0x140000 - 0x14FFFF Core 1 Trace
0x150000 - 0x20FFFF Reserved
0x210000 - 0x21FFFF Core 2 Debug
0x220000 - 0x22FFFF Core 2 CTI
0x230000 - 0x23FFFF Core 2 PMU
0x240000 - 0x24FFFF Core 2 Trace
0x250000 - 0x30FFFF Reserved
0x310000 - 0x31FFFF Core 3 Debug
0x320000 - 0x32FFFF Core 3 CTI
0x330000 - 0x33FFFF Core 3 PMU
0x340000 - 0x34FFFF Core 3 Trace
0x350000 - 0x3FFFFF Reserved
a Indicates the mapped component if present, otherwise reserved.
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