10.11.2 ROM table register summary

The following table shows the offsets from the physical base address of the ROM table.

Table 10-30 ROM table registers

Offset Name Type Description
0x000 ROMENTRY0 RO Core 0 Debug, see ROM entry registers
0x004 ROMENTRY1 RO Core 0 CTI, see ROM entry registers
0x008 ROMENTRY2 RO Core 0 PMU, see ROM entry registers
0x00C ROMENTRY3 RO Core 0 ETM, see ROM entry registers
0x010 ROMENTRY4 RO Core 1 Debug, see ROM entry registers
0x014 ROMENTRY5 RO Core 1 CTI, see ROM entry registers
0x018 ROMENTRY6 RO Core 1 PMU, see ROM entry registers
0x01C ROMENTRY7 RO Core 1 ETM, see ROM entry registers
0x020 ROMENTRY8 RO Core 2 Debug, see ROM entry registers
0x024 ROMENTRY9 RO Core 2 CTI, see ROM entry registers
0x028 ROMENTRY10 RO Core 2 PMU, see ROM entry registers
0x02C ROMENTRY11 RO Core 2 ETM, see ROM entry registers
0x030 ROMENTRY12 RO Core 3 Debug, see ROM entry registers
0x034 ROMENTRY13 RO Core 3 CTI, see ROM entry registers
0x038 ROMENTRY14 RO Core 3 PMU, see ROM entry registers
0x03C ROMENTRY15 RO Core 3 ETM, see ROM entry registers
0x040-0xFCC - RO Reserved, RES0
0xFD0 ROMPIDR4 RO ROM table Debug Peripheral Identification Register 4
0xFD4 ROMPIDR5 RO ROM table Debug Peripheral Identification Register 5-7
0xFD8 ROMPIDR6 RO
0xFDC ROMPIDR7 RO
0xFE0 ROMPIDR0 RO ROM table Debug Peripheral Identification Register 0
0xFE4 ROMPIDR1 RO ROM table Debug Peripheral Identification Register 1
0xFE8 ROMPIDR2 RO ROM table Debug Peripheral Identification Register 2
0xFEC ROMPIDR3 RO ROM table Debug Peripheral Identification Register 3
0xFF0 ROMCIDR0 RO ROM table Debug Component Identification Register 0
0xFF4 ROMCIDR1 RO ROM table Debug Component Identification Register 1
0xFF8 ROMCIDR2 RO ROM table Debug Component Identification Register 2
0xFFC ROMCIDR3 RO ROM table Debug Component Identification Register 3
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