Non-ConfidentialPDF file icon PDF versionARM 100095_0002_04_en
ARM® Cortex®-A72 MPCore Processor Technical Reference ManualRevision r0p2
Home > Performance Monitor Unit > PMU functional description > PMU register interfaces

11.2.4 PMU register interfaces

The Cortex-A72 processor supports access to the Performance Monitor registers from the System registers and a memory-mapped interface. External access to the Performance Monitor registers is also provided with the APB slave interface.
Related information
10.10 External debug interface
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_04_en
Copyright © 2014-2016 ARM. All rights reserved. 
Home > Performance Monitor Unit > PMU functional description > PMU register interfaces