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ARM 100095_0002_04_en
ARM
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Cortex
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-A72 MPCore Processor
Technical Reference Manual
Revision r0p2
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Performance Monitor Unit
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PMU functional description
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11.2.4 PMU register interfaces
The
Cortex-A72
processor supports access to the Performance Monitor registers from the System registers and a memory-mapped interface. External access to the Performance Monitor registers is also provided with the APB slave interface.
Related information
10.10
External debug interface