11.4.2 Performance Monitors Common Event Identification Register 0, EL0

The PMCEID0_EL0 characteristics are:
Purpose
Defines which common architectural and common micro-architectural feature events are implemented.
Usage constraints
The accessibility to the PMCEID0_EL0 by Exception level is:
EL0 (NS) EL0 (S) EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
Config Config RO RO RO RO RO
The external accessibility to the PMCEID0_EL0 by condition code is:
Off DLK OSLK EPMAD SLK Default
Error Error Error Error RO RO
Table 11-1 External register access conditions describes the condition codes.
Configurations
The PMCEID0_EL0 is Common to Secure and Non-secure states and architecturally mapped to:
  • The AArch32 PMCEID0 register.
  • The external PMCEID0_EL0 register.
Attributes
The following figure shows the PMCEID0_EL0 bit assignments
Figure 11-3 PMCEID0_EL0 bit assignments
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The following table shows the PMCEID0_EL0 bit assignments with event implemented or not implemented when the associated bit is set to 1 or 0.
PMCEID1_EL0[31:0] is reserved.

Table 11-5 Common Event Identification Register 0 bit assignments

Bit Name Event number Value Event implemented if bit set to 1 or not implemented if bit set to 0
[31] - 0x1F 0 Reserved, RES0.
[30] CH 0x1E 1 Chain.a An odd-numbered counter increments when an overflow occurs on the preceding even-numbered counter. For even-numbered counters, does not count.
[29] BC 0x1D 1 Bus cycle.
[28] TW 0x1C 1 TTBR write, architecturally executed, condition check pass - write to translation table base.
[27] IS 0x1B 1 Instruction speculatively executed.
[26] ME 0x1A 1 Local memory error.
[25] BA 0x19 1 Bus access.
[24] DC2W 0x18 1 Level 2 data cache Write-Back.
[23] DC2R 0x17 1 Level 2 data cache refill.
[22] DC2A 0x16 1 Level 2 data cache access.
[21] DC1W 0x15 1 Level 1 data cache Write-Back.
[20] IC1A 0x14 1 Level 1 instruction cache access.
[19] MA 0x13 1 Data memory access.
[18] BP 0x12 1 Predictable branch speculatively executed.
[17] CC 0x11 1 Cycle.
[16] BM 0x10 1 Mispredicted or not predicted branch speculatively executed.
[15] UL 0x0F 0 Instruction architecturally executed, condition check pass - unaligned load or store.
[14] BR 0x0E 0 Instruction architecturally executed, condition check pass - procedure return.
[13] BI 0x0D 0 Instruction architecturally executed - immediate branch.
[12] PW 0x0C 0 Instruction architecturally executed, condition check pass - software change of the PC.
[11] CW 0x0B 1 Instruction architecturally executed, condition check pass - write to CONTEXTIDR.
[10] ER 0x0A 1 Instruction architecturally executed, condition check pass - exception return.
[9] ET 0x09 1 Exception taken.
[8] IA 0x08 1 Instruction architecturally executed.
[7] ST 0x07 0 Instruction architecturally executed, condition check pass - store.
[6] LD 0x06 0 Instruction architecturally executed, condition check pass - load.
[5] DT1R 0x05 1 Level 1 data TLB refill.This event is implemented.
[4] DC1A 0x04 1 Level 1 data cache access.
[3] DC1R 0x03 1 Level 1 data cache refill.
[2] IT1R 0x02 1 Level 1 instruction TLB refill.
[1] IC1R 0x01 1 Level 1 instruction cache refill.
[0] SI 0x00 1 Instruction architecturally executed, condition check pass - software increment.
To access the PMCEID0_EL0 in AArch64 state, read or write the register with:
MRS <Xt>, PMCEID0_EL0; Read Performance Monitors Common Event Identification Register 0
To access the PMCEID0 in AArch32 state, read or write the CP15 register with:
MRC p15, 0, <Rt>, c9, c12, 6; Read Performance Monitors Common Event Identification Register 0
The PMCEID0_EL0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xE20.
a See the ARM® Architecture Reference Manual ARMv8 for more information about the chain event.
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