11.5 AArch32 PMU register summary

The PMU counters and their associated control registers are accessible in AArch32 state from the System registers with MCR and MRC instructions for 32-bit registers and MCRR and MRRC for 64-bit registers.

The following table gives a summary of the PMU registers in AArch32 state.
The table also shows the offset address for the AArch32 registers that are accessible from the internal memory-mapped interface or the external debug interface.
See 11.7 Memory-mapped register descriptions for a complete list of registers that are accessible from the internal memory-mapped interface or the external debug interface.

Table 11-6 PMU register summary in AArch32 state

Offset CRn op1 CRm op2 Name Type Width Description
0xE04 c9 0 c12 0 PMCR RW 32-bit 11.4.1 Performance Monitors Control Register, EL0
0xC00     1 PMCNTENSET RW 32-bit Performance Monitors Count Enable Set Register 
0xC20     2 PMCNTENCLR RW 32-bit Performance Monitors Count Enable Clear Register a
0xC80     3 PMOVSR RW 32-bit Performance Monitors Overflow Flag Status Register a
0xCA0     4 PMSWINC WO 32-bit Performance Monitors Software Increment Register a
-     5 PMSELR RW 32-bit Performance Monitors Event Counter Selection Register a
0xE20     6 PMCEID0 RO 32-bit 11.4.2 Performance Monitors Common Event Identification Register 0, EL0
0xE24     7 PMCEID1 RO 32-bit Performance Monitors Common Event Identification Register 1 a
0x0F8 c9 0 c13 0 PMCCNTR[31:0] RW 32-bit Performance Monitors Cycle Count Register a
0x0FC - - - - PMCCNTR[63:32]
- - 0 c9 - PMCCNTR[63:0] 64-bit
- c9 0 c13 1 PMXEVTYPER RW 32-bit Performance Monitors Selected Event Type Register a
0x47C       PMCCFILTR RW 32-bit Performance Monitors Cycle Count Filter Register a
- c9 0 c13 2 PMXEVCNTR RW 32-bit Performance Monitors Selected Event Count Register a
-     c14 0 PMUSERENR RW 32-bit Performance Monitors User Enable Register a
0xC40     1 PMINTENSET RW 32-bit Performance Monitors Interrupt Enable Set Register a
0xC60     2 PMINTENCLR RW 32-bit Performance Monitors Interrupt Enable Clear Register a
0xCC0     3 PMOVSSET RW 32-bit Performance Monitors Overflow Flag Status Set Register a
0x000 c14 0 c8 0 PMEVCNTR0 RW 32-bit Performance Monitors Event Count Registers a
0x008     1 PMEVCNTR1
0x010     2 PMEVCNTR2
0x018     3 PMEVCNTR3
0x020     4 PMEVCNTR4
0x028     5 PMEVCNTR5
0x400     c12 0 PMEVTYPER0 RW 32-bit Performance Monitors Event Type Registers a
0x404     1 PMEVTYPER1
0x408     2 PMEVTYPER2
0x40C     3 PMEVTYPER3
0x410     4 PMEVTYPER4
0x414     5 PMEVTYPER5
0x47C     c15 7 PMCCFILTR RW 32-bit Performance Monitors Cycle Count Filter Register a
a See the ARM® Architecture Reference Manual ARMv8 for more information.
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