11.7.1 Performance Monitors Control Register, EL0

The PMCR_EL0 characteristics are:
Purpose
Configures and controls the counters.
Usage constraints
The external accessibility to the PMCR_EL0 by condition code is:
Off DLK OSLK EPMAD SLK Default
Error Error Error Error RO/WI RW
Table 11-1 External register access conditions describes the access conditions.
Configurations
The PMCR_EL0 is Common to Secure and Non-secure states and architecturally mapped to:
  • The AArch32 PMCR register.
  • The external PMCR_EL0 register.
Attributes
See the register summary in Table 11-7 Memory-mapped PMU register summary.
The following figure shows the PMCR_EL0 bit assignments for a memory-mapped access.
Figure 11-4 PMCR_EL0 bit assignments, memory-mapped view
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The following table shows the PMCR_EL0 bit assignments for a memory-mapped access.

Table 11-8 PMCR_EL0 bit assignments, memory-mapped view

Bits Name Function
[31:7] - Reserved, RES0.
[6] LC The function of these bits is the same as when a System register access occurs. See Table 11-4 PMCR_EL0 bit assignments for a description of these bits.
[5] DP
[4] X
[3] D
[2] C
[1] P
[0] E
The PMCR_EL0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xE04.
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