11.7.5 Performance Monitors Snapshot Status Register

The PMSSR characteristics are:
Provides status information on whether the PMU counters have been captured.
Usage constraints
The external accessibility to the PMSSR by condition code is:
Error Error RO RO RO RO
Table 11-1 External register access conditions describes the condition codes.
A security violation prevents the capture of the event counters.
The external monitor must keep track of whether the snapshot registers were captured by the processor.
To prevent loss of data, software must save and restore the PMU state, including the PMSCR and PMSRR registers, when capturing over a reset or power down.
There is no configuration information for PMSSR.
See the register summary in Table 11-7 Memory-mapped PMU register summary.
The following figure shows the PMSSR bit assignments.
Figure 11-5 PMSSR bit assignments
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The following table shows the PMSSR bit assignments.

Table 11-9 PMSSR bit assignments

Bits Name Function
[31:1] - Reserved, RES0.
[0] NC
No capture. The possible values are:
0PMU counters captured.
1PMU counters not captured.
The NC bit:
  • Is reset to 1 by a Warm reset but overwritten at the first capture.
  • Does not reflect the status of the captured Program Counter Sample registers.
PMSSR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x610.
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