12.6 Cross trigger register descriptions
This section describes the Cortex-A72 processor cross trigger registers.
The Integration Test registers are provided to simplify the
process of verifying the integration of the ECT with other devices
in a CoreSight system. These registers enable direct control of outputs
and the ability to read the value of inputs. You must only use these
registers when the CTIITCTRL.IME bit is set to 1. See the ARM® Architecture
Reference Manual ARMv8 for more information.
This section contains the following subsections: