13.6 Register summary

This section summarizes the ETM registers.

For full descriptions of the ETM registers, see:
  • 10.10 External debug interface, for the IMPLEMENTATION DEFINED registers and the ARM® Embedded Trace Macrocell Architecture Specification, ETMv4, for the other registers.


  • In the following table, access type is described as follows:
    RWRead and write.
    RORead only.
    WOWrite only.
All ETM registers are 32 bits wide. The following table lists all of the registers and their offsets from a base address. The base address is defined by the system integrator when placing the ETM in the Debug-APB memory map.

Table 13-3 ETM register summary

Offset Name Type Description
0x000 - - Reserved
Trace Programming Control Register
0x008 - - Reserved
0x00C TRCSTATR RO Trace Status Register
0x010 TRCCONFIGR RW 13.7.1 Trace Configuration Register
0x014 - - Reserved
0x018 TRCAUXCTLR RW 13.7.2 Trace Auxiliary Control Register
0x01C - - Reserved
0x020 TRCEVENTCTL0R RW 13.7.3 Trace Event Control 0 Register
0x024 TRCEVENTCTL1R RW 13.7.4 Trace Event Control 1 Register
0x028-0x2C - - Reserved
0x030 TRCTSCTLR RW Global Timestamp Control Register
0x034 TRCSYNCPR RW  13.7.5 Trace Synchronization Period Register
0x038 TRCCCCTLR RW 13.7.6 Trace Cycle Count Control Register
0x03C TRCBBCTLR RW Branch Broadcast Control Register
0x040 TRCTRACEIDR RW 13.7.7 Trace ID Register
0x044 -0x07C - - Reserved
0x080 TRCVICTLR RW 13.7.8 ViewInst Main Control Register
0x084 TRCVIIECTLR RW ViewInst Include-Exclude Control Register
0x088 TRCVISSCTLR RW ViewInst Start-Stop Control Register
0x08C -0x0FC - - Reserved
0x100  TRCSEQEVR0 RW Sequencer State Transition Control Register 0
0x104 TRCSEQEVR1 RW Sequencer State Transition Control Register 1
0x108 TRCSEQEVR2 RW Sequencer State Transition Control Register 2
0x10C -0x114 - - Reserved
0x118 TRCSEQRSTEVR RW Sequencer Reset Control Register
0x11C TRCSEQSTR RW Sequencer State Register
0x120 TRCEXTINSELR RW 13.7.9 External Input Select Register
0x124 -0x13C - - Reserved
0x140 TRCCNTRLDVR0 RW Counter Reload Value Register 0
0x144 TRCCNTRLDVR1 RW Counter Reload Value Register 1
0x148-0x14C - - Reserved
0x150 TRCCNTCTLR0 RW Counter Control Register 0
0x154 TRCCNTCTLR1 RW Counter Control Register 1
0x158-0x15C - - Reserved
0x160 TRCCNTVR0 RW Counter Value Register 0
0x164 TRCCNTVR1 RW Counter Value Register 1
0x168-0x16C - - Reserved
0x170 -0x17C - - Reserved
0x180 TRCIDR8 RO 13.7.10 ID Register 8
0x184 TRCIDR9 RO 13.7.11 ID Register 9
0x188 TRCIDR10 RO 13.7.12 ID Register 10
0x18C TRCIDR11 RO 13.7.13 ID Register 11>
0x190 TRCIDR12 RO 13.7.14 ID Register 12
0x194 TRCIDR13 RO 13.7.15 ID Register 13
0x198-0x1BC - - Reserved
0x1C0 TRCIMSPEC0 RW 13.7.16 Implementation Defined Register 0
0x1C4-0x1DC - - Reserved
0x1E0 TRCIDR0 RO 13.7.17 Trace ID Register 0
0x1E4 TRCIDR1 RO 13.7.18 Trace ID Register 1
0x1E8 TRCIDR2 RO 13.7.19 Trace ID Register 2
0x1EC TRCIDR3 RO 13.7.20 Trace ID Register 3
0x1F0 TRCIDR4 RO 13.7.21 Trace ID Register 4
0x1F4 TRCIDR5 RO 13.7.22 Trace ID Register 5
0x1F8 -0x204 - - Reserved
0x208-0x23C TRCRSCTLRn RW 13.7.23 Resource Selection Control Registers, n is 2, 15
0x240-0x27C - - Reserved
0x280 TRCSSCCR0 RW Single-shot Comparator Control Register 0
0x284-0x29C - - Reserved
0x2A0 TRCSSCSR0 RW, RO Single-shot Comparator Status Register 0
0x2A4-0x2FC - - Reserved
0x300 TRCOSLAR WO OS Lock Access Register
0x304 TRCOSLSR RO OS Lock Status Register
0x308 -0x30C - - Reserved
0x310 TRCPDCR RW PowerDown Control Register
0x314 TRCPDSR RO PowerDown Status Register
0x318 -0x3FC - - Reserved
0x400-0x438 TRCACVRn RW Address Comparator Value Register n, n = 0 to 7
0x440-0x47C - - Reserved
0x480-0x4B8 TRCACATRn RW 13.7.24 Address Comparator Access Type Registers, n is 0 to 7
0x4C0-0x5FC - - Reserved
0x600  TRCCIDCVR0 RW 13.7.25 Context ID Comparator Value Register 0
0x608-0x63F - - Reserved
0x640  TRCVMIDCVR0 RW 13.7.26 VMID Comparator Value Register 0
0x648-0x67F - - Reserved
0x680 TRCCIDCCTLR0 RW 13.7.27 Context ID Comparator Control Register 0
0x684-0xED8 - - Reserved
0xEDC TRCITMISCOUT WO 13.7.28 Trace Integration Miscellaneous Outputs Register
0xEE0 TRCITMISCIN RO 13.7.29 Trace Integration Miscellaneous Input Register
0xEE4-0xEE8 - - Reserved
0xEEC TRCITATBDATA0 WO 13.7.30 Trace Integration Test ATB Data Register 0
0xEF0 TRCITATBCTR2 RO 13.7.31 Trace Integration Test ATB Control Register 2
0xEF4 TRCITATBCTR1 WO 13.7.32 Trace Integration Test ATB Control Register 1
0xEF8 TRCITATBCTR0 WO 13.7.33 Trace Integration Test ATB Control Register 0
0xEFC - - Reserved
0xF00 TRCITCTRL RW 13.7.34 Trace Integration Mode Control register
0xF04 -0xF9C - - Reserved
0xFA0 TRCCLAIMSET RW Trace Claim Tag Set register
0xFA4 TRCCLAIMCLR RW Trace Claim Tag Clear register
0xFA8 TRCDEVAFF0 RO 13.7.35 Trace Device Affinity register 0
0xFAC TRCDEVAFF1 RO 13.7.36 Trace Device Affinity register 1
0xFB0 TRCLAR WO Trace Software Lock Access Register
0xFB4 TRCLSR RO Trace Software Lock Status Register
0xFB8 TRCAUTHSTATUS RO Trace Authentication Status register
0xFBC TRCDEVARCH RO Trace Device Architecture register
0xFC0 -0xFC4 - - Reserved
0xFC8 TRCDEVID RO Trace Device ID register
0xFCC TRCDEVTYPE RO Trace Device Type register
0xFD0 TRCPIDR4 RO Trace Peripheral Identification Register 4
0xFD4 TRCPIDR5 RO Trace Peripheral Identification Register 5-7
0xFE0 TRCPIDR0 RO Trace Peripheral Identification Register 0
0xFE4 TRCPIDR1 RO Trace Peripheral Identification Register 1
0xFE8 TRCPIDR2 RO Trace Peripheral Identification Register 2
0xFEC TRCPIDR3 RO Trace Peripheral Identification Register 3
0xFF0 TRCCIDR0 RO Trace Component Identification Register 0
0xFF4 TRCCIDR1 RO Trace Component Identification Register 1
0xFF8 TRCCIDR2 RO Trace Component Identification Register 2
0xFFC TRCCIDR3 RO Trace Component Identification Register 3
Related information
10.11 ROM table
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