13.7.4 Trace Event Control 1 Register

The TRCEVENTCTL1R characteristics are:
Controls the behavior of the events that TRCEVENTCTL0R selects.
Usage constraints
Only accepts writes when the trace unit is disabled.
Available in all configurations.
A 32-bit RW trace register.
The following figure shows the TRCEVENTCTL1R bit assignments.
Figure 13-5 TRCEVENTCL1R bit assignments
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The following table shows the TRCEVENTCTL1R bit assignments.

Table 13-7 TRCEVENTCL1R bit assignments

Bits Name Function
[31:12] - Reserved, RES0.
[11] ATB
ATB trigger enable. This value is:
0ATB trigger is disabled.
[10:4] - Reserved, RES0.
[3:0] INSTEN
Instruction event enable field. Each bit represents an event, n=0-3. If event n occurs when INSTEN[n] is:
0The trace unit does not generate an event element.
1The trace unit generates an event element for event n, in the instruction trace stream.
The TRCEVENTCTL1R can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x024.
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