13.7.7 Trace ID Register

The TRCTRACEIDR characteristics are:
Sets the trace ID for instruction trace.
Usage constraints
Only accepts writes when the trace unit is disabled.
Available in all configurations.
The TRACEID field width is set by TRCIDR5.TRACEIDSIZE.
A 32-bit RW trace register.
The following figure shows the TRCTRACEIDR bit assignments.
Figure 13-8 TRCTRACEIDR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the TRCTRACEIDR bit assignments.

Table 13-10 TRCTRACEIDR bit assignments

Bits Name Function
[31:7] - Reserved, RES0.
[6:0] TRACEID Trace ID field. Sets the trace ID value for instruction trace. The width of this field is 7 bits.
The TRCTRACEIDR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x040.
Related information
13.7.22 Trace ID Register 5
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_04_en
Copyright © 2014-2016 ARM. All rights reserved.