13.7.20 Trace ID Register 3

The TRCIDR3 characteristics are:

Purpose
Indicates:
  • Whether TRCVICTLR is supported.
  • The number of cores available for tracing.
  • If an Exception level supports instruction tracing.
  • The minimum threshold value for instruction trace cycle counting.
  • Whether the synchronization period is fixed.
  • Whether TRCSTALLCTLR is supported and if so whether it supports trace overflow prevention and supports stall control of the core.
Usage constraints
There are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 13.6 Register summary.
The following figure shows the TRCIDR3 bit assignments.
Figure 13-21 TRCIDR3 bit assignments
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The following table shows the TRCIDR3 bit assignments.

Table 13-23 TRCIDR3 bit assignments

Bits Name Function
[31] NOOVERFLOW
Indicates whether TRCSTALLCTLR.NOOVERFLOW is supported. This value is:
0TRCSTALLCTLR.NOOVERFLOW is not supported. STALLCTL is 0.
[30:28] NUMPROC
Indicates the number of cores available for tracing. This value is:
0b000The trace unit can trace one core.
[27] SYSTALL
Indicates whether stall control is supported. This value is:
0The system does not support stall control of the core.
[26] STALLCTL
Indicates whether TRCSTALLCTLR is supported. This value is:
0TRCSTALLCTLR is not supported.
[25] SYNCPR
Indicates whether there is a fixed synchronization period. This value is:
0TRCSYNCPR is read-write so software can change the synchronization period.
[24] TRCERR
Indicates whether TRCVICTLR.TRCERR is supported. This value is:
1TRCVICTLR.TRCERR is supported.
[23:20] EXLEVEL_NS
Each bit controls whether instruction tracing in Non-secure state is supported for the corresponding Exception level. The value is:
0b0111Instruction tracing in Non-secure state is supported for EL0, EL1, and EL2.

Note

The bit to Exception level mapping is:
Bit[20]Exception level 0.
Bit[21]Exception level 1.
Bit[22]Exception level 2.
Bit[23]Always RES0.
[19:16] EXLEVEL_S
Each bit controls whether instruction tracing in Secure state is supported for the corresponding Exception level. The value is:
0b1011Instruction tracing in Secure state is supported for EL0, EL1, and EL3.

Note

The bit to Exception level mapping is:
Bit[16]Exception level 0.
Bit[15]Exception level 1.
Bit[14]Always RES0.
Bit[13]Exception level 3.
[15:12] - Reserved, RES0.
[11:0] CCITMIN
The minimum value that can be programmed in TRCCCCTLR.THRESHOLD. This value is:
0x004Minimum value for cycle counting in the instruction trace.
The TRCIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x1EC.
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