13.7.23 Resource Selection Control Registers

The TRCRSCTLRn characteristics are:
Purpose
Controls the selection of the resources in the trace unit.

Note

The range of n for TRCRSCTLRn is 2 to 15.
Usage constraints
  • Only accepts writes when the trace unit is disabled.
  • If software selects an non-implemented resource then constrained UNPREDICTABLE behavior of the resource selector occurs. The resource selector might activate unexpectedly or might not activate. Reads of the TRCRSCTLRn might return UNKNOWN.
Configurations
Resource selectors are implemented in pairs and there are eight pairs of TRCRSCTLR registers implemented, set by TRCIDR4.NUMRSPAIR. Each odd numbered resource selector is part of a pair with the even numbered resource selector that is numbered as one less than it. For example, resource selectors 2 and 3 form a pair.
Resource selector pair 0 is always implemented and is reserved. Resource selector zero always returns FALSE, and resource selector one always returns TRUE.
Attributes
A 32-bit RW trace register.
The following figure shows the TRCRSCTLRn bit assignments.
Figure 13-24 TRCSCTLR
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The following table shows the TRCRSCTLRn bit assignments.

Table 13-26 TRCSCTLRn bit assignments

Bits Name Function
[31:22] - Reserved, RES0.
[21] PAIRINV
Controls whether the combined result from a resource pair is inverted when n is 2, 4, 6, 8, 10, 12, or 14. The possible values are:
0The combined result is not inverted.
1The combined result is inverted.
PAIRINV is RES0 when n is 3, 5, 7, 9, 11, 13, or 15.
[20] INV
Controls whether the resource, that GROUP and SELECT selects, is inverted. The possible values are:
0The selected resource is not inverted.
1The selected resource is inverted.
[19] - Reserved, RES0.
[18:16] Group Selects a group of resources. See the ARM® Embedded Trace Macrocell Architecture Specification, ETMv4 for more information.
[15:8] - Reserved, RES0.
[7:0] Select Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group. See the ARM® Embedded Trace Macrocell Architecture Specification, ETMv4 for more information.
The TRCRSCTLRn can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x208-023C.
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