14.4.3 Media and VFP Feature Register 0, EL1

The MVFR0_EL1 characteristics are:
Purpose
The MVFR0_EL1 must be interpreted with the MVFR1_EL1 and the MVFR2_EL1 to describe the features provided by the Advanced SIMD and FP functions.
Usage constraints
The accessibility to the MVFR0_EL1 in AArch64 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
The accessibility to the MVFR0 in AArch32 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- Config RO Config Config RO
Configurations
MVFR0_EL1 is:
  • Common to Secure and Non-secure states
  • Architecturally mapped to AArch32 MVFR0 register.
Attributes
The following figure shows the MVFR0_EL1 bit assignments.
Figure 14-3 MVFR0_EL1 bit assignments
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The following table shows the MVFR0_EL1 bit assignments.

Table 14-5 MVFR0_EL1 bit assignments

Bits Name Function
[31:28] FPRound
Indicates the rounding modes supported by the FP floating-point hardware:
0x1All rounding modes supported.
[27:24] FPShVec
Indicates the hardware support for FP short vectors:
0x0Not supported.
[23:20] FPSqrt
Indicates the hardware support for FP square root operations:
0x1Supported.
[19:16] FPDivide
Indicates the hardware support for FP divide operations:
0x1Supported.
[15:12] FPTrap
Indicates whether the FP hardware implementation supports exception trapping:
0x0Not supported.
[11:8] FPDP
Indicates the hardware support for FP double-precision operations:
0x2Supported, VFPv3 or greater.
See the ARM® Architecture Reference Manual ARMv8 for more information.
[7:4] FPSP
Indicates the hardware support for FP single-precision operations:
0x2Supported, VFPv3 or greater.
See the ARM® Architecture Reference Manual ARMv8 for more information.
[3:0] SIMDReg
Indicates support for the Advanced SIMD register bank:
0x232× 64-bit registers supported.
See the ARM® Architecture Reference Manual ARMv8 for more information.
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