14.6.2 Floating-point Status and Control Register

The FPSCR characteristics are:
Purpose
Provides floating-point system status information and control.
Usage constraints
The accessibility to the FPSCR by Exception level is:
EL0 (NS) EL0 (S) EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
Config RW Config RW Config Config RW
Configurations
The FPSCR is Common to Secure and Non-secure states.
The named fields in this register map to the equivalent fields in the AArch64 FPCR and FPSR.
Attributes
See the register summary in Table 14-9 AArch32 Advanced SIMD and Floating-point System registers.
The following figure shows the FPSCR bit assignments.
Figure 14-8 FPSCR bit assignments
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The following table shows the FPSCR bit assignments.

Table 14-11 FPSCR bit assignments

Bits Field Function
[31] N
FP Negative condition code flag.
Set to 1 if a FP comparison operation produces a less than result.
[30] Z
FP Zero condition code flag.
Set to 1 if a FP comparison operation produces an equal result.
[29] C
FP Carry condition code flag.
Set to 1 if a FP comparison operation produces an equal, greater than, or unordered result.
[28] V
FP Overflow condition code flag.
Set to 1 if a FP comparison operation produces an unordered result.
[27] QC
Cumulative saturation bit.
This bit is set to 1 to indicate that an Advanced SIMD integer operation has saturated after 0 was last written to this bit.
[26] AHP
Alternative Half-Precision control bit:
0IEEE half-precision format selected.
1Alternative half-precision format selected.
[25] DN
Default NaN mode control bit:
0NaN operands propagate through to the output of a floating-point operation.
1Any operation involving one or more NaNs returns the Default NaN.
The value of this bit only controls FP arithmetic. In AArch32 state, Advanced SIMD arithmetic always uses the Default NaN setting, regardless of the value of the DN bit.
[24] FZ
Flush-to-zero mode control bit:
0Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
1Flush-to-zero mode enable.
The value of this bit only controls FP arithmetic. In AArch32 state, Advanced SIMD arithmetic always uses the Flush-to-zero setting, regardless of the value of the FZ bit.
[23:22] RMode
Rounding Mode control field:
0b00Round to Nearest (RN) mode.
0b01Round towards Plus Infinity (RP) mode.
0b10Round towards Minus Infinity (RM) mode.
0b11Round towards Zero (RZ) mode.
The specified rounding mode is used by almost all FP floating-point instructions. In AArch32 state, Advanced SIMD arithmetic always uses the Round to Nearest setting, regardless of the value of the RMode bits.
[21:20] Stride
Reserved, RES0.
[19] - Reserved, RES0.
[18:16] Len
Reserved, RES0.
[15:8] -
Reserved, RES0.
[7] IDC
Input Denormal cumulative exception bit. This bit is set to 1 to indicate that the Input Denormal exception has occurred since 0 was last written to this bit.
[6:5] -
Reserved, RES0.
[4] IXC Inexact cumulative exception bit. This bit is set to 1 to indicate that the Inexact exception has occurred since 0 was last written to this bit.
[3] UFC Underflow cumulative exception bit. This bit is set to 1 to indicate that the Underflow exception has occurred since 0 was last written to this bit.
[2] OFC Overflow cumulative exception bit. This bit is set to 1 to indicate that the Overflow exception has occurred since 0 was last written to this bit.
[1] DZC Division by Zero cumulative exception bit. This bit is set to 1 to indicate that the Division by Zero exception has occurred since 0 was last written to this bit.
[0] IOC Invalid Operation cumulative exception bit. This bit is set to 1 to indicate that the Invalid Operation exception has occurred since 0 was last written to this bit.
Related information
14.4.1 Floating-point Control Register
14.4.2 Floating-point Status Register
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