A.2 Clock signals

The following table shows the clock and clock enable signals.

Table A-1 Clock and clock enable signals

Signal Type Description
CLK Input Global clock.
Input Global clock enable. This signal can only be deasserted when all the cores in the processor device and the L2 are in WFI low-power state, and the ACE/CHI and ACP interfaces are idle.
Related information
2.3 Clocking and resets
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