A.3 Reset signals

The following table shows the reset and reset control signals.

Table A-2 Reset signals

Signal Type Description
nCPUPORESET[N:0] Input
Individual processor powerup resets:
0Apply reset to the processor including Debug, ETM, breakpoint and watchpoint logic.
1Do not apply reset to the processor.
nCORERESET[N:0] Input
Individual processor reset excluding Debug and ETM:
0Apply reset to the processor excluding Debug, ETM, breakpoint and watchpoint logic.
1Do not apply reset to the processor.
WARMRSTREQ[N:0] Output
Individual processor Warm reset request:
0Do not apply Warm reset to processor.
1Apply Warm reset to processor.
This output is controlled by Reset request bit in the Reset Management Register (RMR or RMR_EL3).
nL2RESET Input
L2 reset:
0Apply reset to shared L2 memory system controller.
1Do not apply reset to shared L2 memory system controller.
L2RSTDISABLE Input
Disable automatic L2 cache invalidate at reset:
0L2 cache is reset by hardware.
1L2 cache is not reset by hardware.
Related information
2.3.2 Resets
2.3 Clocking and resets
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