A.5 GIC CPU interface signals

The following table shows the Generic Interrupt Controller (GIC) CPU interface signals.

Table A-4 GIC CPU interface signals

Signal Type Description
nIRQ[N:0] Input
Individual core IRQ request input. Active-LOW, interrupt request:
0Activate IRQ request.
1Do not activate IRQ request.
The processor treats nIRQ as level-sensitive. nIRQ must remain asserted until the processor acknowledges the interrupt.
This signal is only used when IRQ is in bypass mode, and used as legacy IRQ.
nFIQ[N:0] Input
Individual processor FIQ request input. Active-LOW, FIQ request:
0Activate FIQ request.
1Do not activate FIQ request.
The processor treats nFIQ as level-sensitive. nFIQ must remain asserted until the processor acknowledges the interrupt.
This signal is only used when FIQ is in bypass mode, and used as legacy FIQ.
nVIRQ[N:0] Input
Individual processor virtual IRQ request input. Active-LOW, virtual IRQ request:
0Activate virtual IRQ request.
1Do not activate virtual IRQ request.
The processor treats nVIRQ as level-sensitive. nVIRQ must remain asserted until the processor acknowledges the interrupt.
nVFIQ[N:0] Input
Individual processor virtual FIQ request input. Active-LOW, virtual FIQ request:
0Activate virtual FIQ request.
1Do not activate virtual FIQ request.
The processor treats nVFIQ as level-sensitive. nVFIQ must remain asserted until the processor acknowledges the interrupt.
nSEI[N:0] Input
Individual processor System Error Interrupt request. Active-LOW, SEI request:
0Activate SEI request.
1Do not activate SEI request.
The processor treats nSEI as edge-sensitive. The nSEI signal must be sent as a pulse to the processor.
nREI[N:0] Input
Individual core RAM Error Interrupt request. Active-LOW, REI request.
0Activate REI request. Reports an asynchronous RAM error in the system.
1Do not activate REI request.
The processor treats nREI as edge-sensitive. nREI must be sent as a pulse to the processor.
nVSEI[N:0] Input
Individual core virtual System Error Interrupt request. Active-LOW, virtual SEI request:
0Activate virtual SEI request.
1Do not activate virtual SEI request.
The processor treats nVSEI as edge-sensitive. nVSEI must be sent as a pulse to the processor.
nVCPUMNTIRQ[N:0] Output Individual core virtual CPU interface maintenance interrupt request. Processor N sets this signal LOW to issue a maintenance interrupt request to the external Distributor.
PERIPHBASE[43:18] Input Specifies the base address for the GIC registers. This value is sampled into the Configuration Base Address Register (CBAR) at reset.
GICCDISABLE Input
Disables the GIC CPU interface logic and routes the legacy nIRQ, nFIQ, nVIRQ, and nVFIQ signals directly to the processor:
0Enable the GIC CPU interface logic.
1Disable the GIC CPU interface logic.
This signal is only sampled during powerup reset of the processor.
AXI4 Stream protocol signals:a
ICDTVALID Input When HIGH it indicates that the Distributor is driving a valid transfer.
ICDTREADY Output When HIGH it indicates that the processor can accept a transfer in the current cycle.
ICDTDATA[15:0] Input The primary payload that passes data from the Distributor to the processor.
ICDTLAST Input When HIGH it indicates the boundary of a packet.
ICDTDEST[1:0] Input Provides routing information for the data stream from the Distributor.
ICCTVALID Output When HIGH it indicates that the processor is driving a valid transfer.
ICCTREADY Input When HIGH it indicates that the Distributor can accept a transfer in the current cycle.
ICCTDATA[15:0] Output The primary payload that passes data from the processor to the Distributor.
ICCTLAST Output When HIGH it indicates the boundary of a packet.
ICCTID[1:0] Output The data stream identifier that indicates different streams of data.
Related information
4.3.70 Configuration Base Address Register, EL1
4.5.24 Configuration Base Address Register
GICCDISABLE bypass mode
a See the ARM® AMBA® AXI4-Stream Protocol Specification for more information.
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