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Home > Signal Descriptions > ACP interface signals > Clock and configuration signals |
Table A-27 Clock and configuration signals
Signal | Type | Description |
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ACLKENS | Input | ACP clock enable. |
AINACTS | Input | ACP inactive control. When this signal is HIGH, the ACP stops accepting requests by deasserting ARREADYS and AWREADYS. When AINACTS is asserted, the SoC must not assert ARVALIDS, AWVALIDS, or WVALIDS. |