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ARM® Cortex®-A72 MPCore Processor Technical Reference ManualRevision r0p2
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A.11.1 Clock and configuration signals

The following table shows the clock and configuration signals for the ACP interface.

Table A-27 Clock and configuration signals

Signal Type Description
ACLKENS Input ACP clock enable.
AINACTS Input ACP inactive control. When this signal is HIGH, the ACP stops accepting requests by deasserting ARREADYS and AWREADYS. When AINACTS is asserted, the SoC must not assert ARVALIDS, AWVALIDS, or WVALIDS.
Related information
2.3.1 Clocks
2.4.1 Dynamic power management
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