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ARM® Cortex®-A72 MPCore Processor Technical Reference ManualRevision r0p2
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A.12.1 APB interface signals

The following table shows the APB interface signals.

Table A-33 APB interface signals

Signal Type Description
PCLKDBG Input APB clock.
PCLKENDBG Input APB clock enable.
nPRESETDBG Input Active-LOW APB reset:
0Reset APB.
1Do not reset APB.
PSELDBG Input
Debug registers select:
0Debug registers not selected.
1Debug registers selected.
PADDRDBG[21:2] Input APB address bus bits[21:2].
PADDRDBG31 Input
APB address bus bit[31]:
0Not an external debugger access.
1External debugger access.
PENABLEDBG Input Indicates the second and subsequent cycles of an APB transfer.
PWRITEDBG Input
APB read or write signal:
0Reads from APB.
1Writes to APB.
PWDATADBG[31:0] Input APB write data bus.
PRDATADBG[31:0] Output APB read data bus.
PREADYDBG Output APB slave ready. An APB slave can assert PREADYDBG to extend a transfer by inserting wait states.
PSLVERRDBG Output
APB slave transfer error:
0No transfer error.
1Transfer error.
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