A.12.3 Miscellaneous debug signals

The following table shows the miscellaneous debug signals.

Table A-35 Miscellaneous debug signals

Signal Type Description
DBGROMADDR[43:12] Input
Specifies bits[43:12] of the top-level ROM table Physical Address.
If the address cannot be determined, tie this signal LOW.
This signal is only sampled during powerup reset of the processor.
DBGROMADDRV Input
Valid signal for DBGROMADDR.
If the address cannot be determined, tie this signal LOW.
This signal is only sampled during powerup reset of the processor.
DBGACK[N:0] Output
Debug acknowledge:
0Debug not acknowledged.
1Debug acknowledged.
nCOMMIRQ[N:0] Output
Communications channel receive or transmit interrupt request, active LOW:
0Receive section data transfer register is full or transmit section data transfer register is empty.
1
Either or both:
  • The receive section data transfer register is empty.
  • The transmit section data transfer register is empty.
COMMRX[N:0] Output
Communications channel receive. Receive portion of Data Transfer Register full flag:
0
Empty.
1Full.
COMMTX[N:0] Output
Communication channel transmit. Transmit portion of Data Transfer Register empty flag:
0Full.
1Empty.
EDBGRQ[N:0] Input
External debug request:
0No external debug request.
1External debug request.
The processor treats the EDBGRQ input as level-sensitive. The EDBGRQ input must be asserted until the processor asserts DBGACK.
DBGRSTREQ[N:0] Output
Warm reset request:
0Warm reset is not requested.
1Request Warm reset.
This output is controlled by Warm reset request bit in External Debug Power/Reset Control Register, EDPRCR.
DBGNOPWRDWN[N:0] Output
No powerdown request. On a powerdown request:
0The SoC power controller powers down the processor.
1The SoC power controller does not power down the processor.
DBGPWRDUP[N:0] Input
Processor power status:
0Processor is not powered up.
1Processor is powered up.
DBGPWRUPREQ[N:0] Output
Processor powerup request:
0No request for processor power up.
1Request for processor power up.
DBGL1RSTDISABLE Input
Disable L1 data cache and L2 snoop tag RAM automatic invalidate on reset functionality.
0Enable automatic invalidation of L1 data cache and L2 snoop tag RAMs on reset.
1Disable automatic invalidation of L1 data cache and L2 snoop tag RAMs on reset
This signal is sampled only during reset of the processor.
Related information
WARMRSTREQ and DBGRSTREQ
External debug over powerdown
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