A.16.1 DFT signals

The following table shows the DFT interface signals.

Table A-40 DFT interface signals

Signal Type Description
DFTCLKBYPASS Input Bypasses the strobe clock register to the L2 RAMs, forcing the L2 RAMs to be tested using CLK as the source clock
DFTCRCLKDISABLE[N:0] Input Disables processor clock grid
DFTL2CLKDISABLE Input Disables L2 clock grid
DFTMCPHOLD Input Disables multi-cycle paths on RAM interfaces
DFTRAMHOLD Input Disables the RAM chip selects during scan shift
DFTRSTDISABLE Input Disables internal synchronized reset during scan shift
DFTSE Input Scan shift enable, forces on the clock grids during scan shift
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