B.2.31 Accessing reserved debug registers

The processor deviates from the preferred behavior because the hardware cost to decode some of the addresses in the debug power domain is significant.
The processor behavior is:
  1. For reserved debug registers 0x000 - 0xCFC and reserved Performance Monitors registers 0x000 - 0xF00, the response is CONSTRAINED UNPREDICTABLE Error, when any of the following apply:
    OffCore power domain is either completely off, or in a low-power state where the Core power domain registers are not accessible.
    DLKDoubleLockStatus() is TRUE, OS double-lock is locked, that is, EDPRSR.DLK is 1.
    OSLKOSLSR_EL1.OSLK is 1, OS Lock is locked.
  2. For reserved debug registers in the address ranges 0x400 - 0x4FC and 0x800 - 0x8FC, the response is CONSTRAINED UNPREDICTABLE Error when the conditions in 1 do not apply and:
    EDADAllowExternalDebugAccess() is FALSE, external debug access is disabled.
  3. For reserved Performance Monitor registers in the address ranges 0x000 - 0x0FC and 0x400 - 0x47C, the response is CONSTRAINED UNPREDICTABLE Error when the conditions in 1 and 2 do not apply but the following condition applies:
    EPMADAllowExternalPMUAccess() is FALSE (external Performance Monitors access is disabled).
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