10.10.3 DBGL1RSTDISABLE debug signal

When set HIGH, the DBGL1RSTDISABLE input signal disables the automatic hardware controlled invalidation of the L1 data cache after the processor is reset using nCORERESET or nCPUPORESET. It also disables the automatic hardware-controlled invalidation of the L2 snoop tag RAMs after the L2 is reset using nL2RESET.

The DBGL1RSTDISABLE must be used only to assist debug of an external watchdog triggered reset by allowing the contents of the L1 data cache before the reset to be observable after the reset. If reset is asserted, while an L1 data cache eviction or L1 data cache fetch is performed, the accuracy of those cache entries is not guaranteed. Similarly, the contents of the L2 snoop tag RAMs might be observed following reset of the L2 if DBGL1RSTDISABLE is asserted before resetting the L2.
You must not use the DBGL1RSTDISABLE signal to disable automatic hardware-controlled invalidation of the L1 data cache or the L2 snoop tag RAMs in normal processor powerup sequences. This is because synchronization of the L1 data cache invalidation sequence with the duplicate L1 tags in the Level 2 Memory System is not guaranteed.
The DBGL1RSTDISABLE signal applies to all processors in the multiprocessor. Each processor samples the signal when nCORERESET or nCPUPORESET is asserted. The L2 samples the signal when nL2RESET is asserted.
If the functionality offered by the DBGL1RSTDISABLE input signal is not required, the input must be tied to LOW.
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