C.1 Revisions

Table C-1 Issue 01

Change
Location
Affects
First release
-
-

Table C-2 Issue 02

Change
Location
Affects
Updated for support of 4MB L2 cache size
Throughout document
r0p1
Added configuration options for up to two L2 Data RAM slices
Throughout document
r0p1
L1 hardware prefetcher terminology clarified to load-store hardware prefetcher
Throughout document
r0p1
Updated Main ID Register Value (MIDR) Throughout document
r0p1

Table C-3 Issue 03

Change
Location
Affects
Updated bit [23] of L2 Auxiliary Control Register, EL1
r0p2
Updated bit [41] of CPU Auxiliary Control Register, EL1
r0p2

Table C-4 Issue 04

Change
Location
Affects
Updated bits to write to disable L2 prefetch
r0p2
Corrected revision bit value.
r0p2
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