Arm® MPS2 and MPS2+ FPGA Prototyping Boards Technical Reference Manual

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1 Introduction
1.1 Precautions
1.1.1 Ensuring safety
1.1.2 Operating temperature
1.1.3 Preventing damage
1.1.4 Encryption key
1.2 About the MPS2 and MPS2+ FPGA Prototyping Boards
1.3 Location of components on the MPS2 FPGA Prototyping Board
1.4 Location of components on the MPS2+ FPGA Prototyping Board
2 Hardware Description
2.1 Overview of the MPS2 and MPS2+ hardware
2.2 Clocks
2.3 Powerup, powerdown, and resets
2.4 User expansion port
2.5 USB 2.0 Full Speed interface
2.6 SPI interface
2.7 UART interface
2.8 VGA and CLCD interfaces
2.9 Audio interface
2.10 Ethernet interface
2.11 User switches and user LEDs
2.12 External user memory
2.13 MCC FPGA serial interface
2.13.1 Serial Configuration Controller (SCC)
2.13.2 SCC READ and WRITE operations
2.13.3 SCC READ and WRITE timings
2.14 Power
2.15 Debug and trace
2.15.1 Overview of FPGA debug and trace systems
2.15.2 F-JTAG
2.15.3 P-JTAG
2.15.4 4-bit Trace
2.15.5 16-bit Trace
2.15.6 Serial Wire Debug
2.15.7 CMSIS-DAP FPGA debug
2.16 Minimum design settings for board operation
3 Configuration
3.1 Overview of the configuration process
3.2 Remote USB operation
3.3 Configuration system
3.4 Powerup and configuration process
3.5 Reset push buttons
3.5.1 ON/OFF/Soft RESET button
3.5.2 Hardware RESET button
3.6 Configuration files
3.6.1 Overview of configuration files and microSD card directory structure
3.6.2 config.txt generic board configuration file
3.6.3 Contents of the MB directory
3.6.4 Contents of the SOFTWARE directory
4 Programmers Model
4.1 About this programmers model
4.2 Memory map
4.3 Register summary
4.4 SCC register descriptions
4.4.1 Overview of SCC registers
4.4.2 SCC_CFG0 Register
4.4.3 SCC_CFG1 Register
4.4.4 SCC_CFG3 Register
4.4.5 SCC_CFG4 Register
4.4.6 SCC_DLL Register
4.4.7 SCC_AID Register
4.4.8 SCC_ID Register
4.5 System configuration registers
4.5.1 Overview of system configuration registers
4.5.2 SYS_CFGDATA_RTN Register
4.5.3 SYS_CFGDATA_OUT Register
4.5.4 SYS_CFGCTRL Register
4.5.5 SYS_CFGSTAT Register
5 Signal Descriptions
5.1 Debug connectors
5.1.1 JTAG 14 connector
5.1.2 JTAG 20 connector
5.1.3 CoreSight 10 connector
5.1.4 CoreSight 20 connector
5.1.5 MICTOR 38 connector
5.2 Expansion connectors
5.3 CLCD connector
5.4 USB 2.0 connector
5.5 UART connector
5.6 SPI connector
5.7 VGA connector
5.8 Audio connectors
5.9 Ethernet connector
5.10 12V power connector
A Specifications
A.1 Electrical specification
A.1.1 FPGA current requirements
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
DDI0525A 20 December 2013 Non-Confidential First issue of TRM
DDI0525B 1 October 2014 Non-Confidential Second issue of TRM
DDI0525C 10 November 2014 Non-Confidential Third issue of TRM
0100-03 2 April 2015 Non-Confidential Fourth issue of TRM
0200-04 2 September 2015 Non-Confidential Fifth issue of TRM
0200-05 11 January 2016 Non-Confidential Sixth issue of TRM
0200-06 18 July 2016 Non-Confidential Seventh issue of TRM
0200-07 27 April 2018 Non-Confidential Eighth issue of TRM
0200-08 15 February 2019 Non-Confidential Ninth issue of TRM

Non-Confidential Proprietary Notice

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Confidentiality Status

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Product Status

The information in this document is Final, that is for a developed product.

Web Address

Conformance Notices

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

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The system should be powered down when not in use.

It is recommended that ESD precautions be taken when handling development boards.

The board generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. There is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • Ensure attached cables do not lie across the target board
  • Reorient the receiving antenna
  • Increase the distance between the equipment and the receiver
  • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected
  • Consult the dealer or an experienced radio/TV technician for help


It is recommended that wherever possible shielded interface cables be used.
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