ARM® Versatile™ Express Juno Development Platform (V2M-Juno) Technical Reference Manual

Table of Contents

About this book
Product revision status
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1 Introduction
1.1 Precautions
1.1.1 Ensuring safety
1.1.2 Preventing damage
1.2 About the Versatile™ Express Juno Development Platform
1.3 Location of components on the V2M‑Juno motherboard
1.4 Connectors on front and rear panels
2 Hardware Description
2.1 Overview of V2M-Juno motherboard hardware
2.2 Juno ARM Development Platform SoC
2.3 External power
2.4 Power management and temperature protection
2.4.1 Power control and Dynamic Voltage and Frequency Scaling (DVFS)
2.4.2 Calibrating the PVT sensor
2.5 Clocks
2.5.1 Overview of clocks
2.5.2 Juno SoC andV2M‑Juno motherboard clocks
2.5.3 IOFPGA clocks
2.6 Resets
2.6.1 Reset push buttons
2.6.2 Reset architecture
2.6.3 Reset sequence
2.7 Thin Links
2.7.1 Overview of Thin Links AXI master and slave interfaces
2.7.2 Thin Links master interface
2.7.3 Thin Links slave interface
2.9 HDLCD interface
2.10 Interrupts
2.11 USB 2.0 interface
2.12 SMC 10/100 Ethernet interface
2.13 UART interface
2.14 Keyboard and mouse interface
2.15 Additional user key entry
2.16 Debug and trace
3 Configuration
3.1 Overview of the V2M‑Juno motherboard configuration system
3.2 Configuration process and operating modes
3.2.1 Transitions between operating modes
3.2.2 Powerup and configuration sequence
3.2.3 Powerdown sequence
3.2.4 Sleep‑state sequence
3.2.5 Wake-up sequence
3.3 Configuration files
3.3.1 Overview of configuration files and microSD card directory structure
3.3.2 config.txt generic motherboard configuration file
3.3.3 Contents of the MB directory
3.3.4 Contents of the SITE1 directory
3.3.5 Contents of the SITE2 directory
3.3.6 Contents of the SOFTWARE directory
3.4 Configuration switches
3.4.1 Use of configuration switches
3.4.2 Remote UART configuration
3.5 Use of reset push buttons
3.5.1 Use of ON/OFF/Soft Reset button
3.5.2 Use of Hardware Reset button
3.6 Command-line interface
3.6.1 Overview of the V2M‑Juno motherboard MCC command-line interface
3.6.2 Overview of the LogicTile daughterboard command-line interface
3.6.3 MCC main command menu
3.6.4 MCC debug menu
3.6.5 EEPROM menu
4 Programmers Model
4.1 About this programmers model
4.2 V2M‑Juno motherboard memory maps
4.2.1 Juno SoC top-level application and SMC interface memory maps
4.2.2 IOFPGA system peripherals memory map
4.2.3 DDR3L memory map
4.2.4 Additional Juno ARM Development Platform SoC memory maps
4.3 APB system registers
4.3.1 APB system register summary
4.3.2 SYS_ID Register
4.3.3 SYS_SW Register
4.3.4 SYS_LED Register
4.3.5 SYS_100HZ Register
4.3.6 SYS_FLAG Registers
4.3.7 SYS_CFGSW Register
4.3.8 SYS_24MHZ Register
4.3.9 SYS_MISC Register
4.3.10 SYS_PROC_ID0 Register
4.3.11 SYS_PROC_ID1 Register
4.3.12 SYS_FAN_SPEED Register
4.3.13 SP810_CTRL Register
4.4 APB system configuration registers
4.4.1 APB system configuration register summary
4.4.2 SYS_CFGDATA Register
4.4.3 SYS_CFGCTRL Register
4.4.4 SYS_CFGSTAT Register
4.5 APB energy meter registers
4.5.1 APB energy register summary
4.5.2 SYS_I_SYS Register
4.5.3 SYS_I_A57 Register
4.5.4 SYS_I_A53 Register
4.5.5 SYS_I_GPU Register
4.5.6 SYS_V_SYS Register
4.5.7 SYS_V_A57 Register
4.5.8 SYS_V_A53 Register
4.5.9 SYS_V_GPU Register
4.5.10 SYS_POW_SYS Register
4.5.11 SYS_POW_A57 Register
4.5.12 SYS_POW_A53 Register
4.5.13 SYS_POW_GPU Register
4.5.14 SYS_ENM_SYS Register
4.5.15 SYS_ENM_A57 Register
4.5.16 SYS_ENM_A53 Register
4.5.17 SYS_ENM_GPU Register
A.1 Signal Descriptions
A.1.1 Debug connectors
A.1.2 Configuration 10Mbps Ethernet and dual‑USB connector
A.1.3 Dual-USB connector
A.1.4 SMC 10/100 Ethernet connector
A.1.5 Configuration USB connector
A.1.6 Header connectors
A.1.7 Keyboard and Mouse Interface (KMI) connector
A.1.8 HDMI connectors
A.1.9 Dual‑UART connector
A.1.10 Secure keyboard and user push buttons connector
A.1.11 ATX power connector
B.2 Prototype V2M‑Juno motherboard
B.2.1 Overview of the prototype V2M‑Juno motherboard
B.2.2 Location of components on the prototype V2M‑Juno motherboard
B.2.3 IOFPGA internal architecture with SMC USB ports
B.2.4 SMC memory map of the prototype V2M‑Juno motherboard
B.2.5 SMC USB 2.0 connectors
C.3 Specifications
C.3.1 Electrical specification
D.4 Revisions
D.4.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
DDI0524A 24 June 2014 Non-Confidential First issue of TRM
DDI0524B 1 October 2014 Non-Confidential Second issue of TRM
DDI0524C 19 January 2015 Non-Confidential Third issue of TRM
0000-03 7 April 2015 Non-Confidential Fourth issue of TRM
0000-04 31 March 2016 Non-Confidential Fifth issue of TRM
0000-05 15 July 2016 Non-Confidential Sixth issue of TRM

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Confidentiality Status

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Web Address

Conformance Notices

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

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The system should be powered down when not in use.
It is recommended that ESD precautions be taken when handling Versatile™ Express boards.
The motherboard generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. There is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:
  • Ensure attached cables do not lie across the target board
  • Reorient the receiving antenna
  • Increase the distance between the equipment and the receiver
  • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected
  • Consult the dealer or an experienced radio/TV technician for help


It is recommended that wherever possible shielded interface cables be used.
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