Arm® Versatile™ Express Juno r2 Development Platform (V2M-Juno r2) Technical Reference Manual

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1 Introduction
1.1 Precautions
1.1.1 Ensuring safety
1.1.2 Preventing damage
1.2 About the Versatile™ Express Juno r2 Development Platform
1.3 Location of components on the V2M‑Juno r2 motherboard
1.4 Connectors on front and rear panels
2 Hardware Description
2.1 Overview of V2M‑Juno r2 motherboard hardware
2.2 Juno r2 Arm® Development Platform SoC
2.3 External power
2.4 Power management and temperature protection
2.4.1 Power control and Dynamic Voltage and Frequency Scaling (DVFS)
2.4.2 PVT sensor
2.5 Clocks
2.5.1 Overview of clocks
2.5.2 Juno r2 SoC and V2M‑Juno r2 motherboard clocks
2.5.3 IOFPGA clocks
2.6 Resets
2.6.1 Reset push buttons
2.6.2 Reset architecture
2.6.3 Reset sequence
2.7 Thin Links
2.7.1 Overview of Thin Links master and slave interfaces
2.7.2 Thin Links master interface
2.7.3 Thin Links slave interface in non‑coherent mode
2.7.4 Thin Links slave interface in coherent mode
2.9 HDLCD interface
2.10 Interrupts
2.11 USB 2.0 interface
2.12 SMC 10/100 Ethernet interface
2.13 UART interface
2.14 PCI Express system
2.14.1 Overview of PCI Express system
2.14.2 PCI Express expansion slots
2.14.3 SATA 2.0 ports
2.14.4 Gigabit Ethernet port
2.15 Keyboard and mouse interface
2.16 Additional user key entry
2.17 Debug and trace
3 Configuration
3.1 Overview of the V2M‑Juno r2 motherboard configuration system
3.2 Configuration process and operating modes
3.2.1 Transitions between operating modes
3.2.2 Powerup and configuration sequence
3.2.3 Powerdown sequence
3.2.4 Sleep‑state sequence
3.2.5 Wake‑up sequence
3.3 Configuration files
3.3.1 Overview of configuration files and microSD card directory structure
3.3.2 config.txt generic motherboard configuration file
3.3.3 Contents of the MB directory
3.3.4 Contents of the SITE1 directory
3.3.5 Contents of the SITE2 directory
3.3.6 Contents of the SOFTWARE directory
3.4 Configuration switches
3.4.1 Use of configuration switches
3.4.2 Remote UART configuration
3.5 Use of reset push buttons
3.5.1 Use of ON/OFF/Soft Reset button
3.5.2 Use of Hardware Reset button
3.6 Command-line interface
3.6.1 Overview of the V2M‑Juno r2 motherboard MCC command-line interface
3.6.2 Overview of the LogicTile daughterboard command-line interface
3.6.3 MCC main command menu
3.6.4 MCC debug menu
3.6.5 EEPROM menu
4 Programmers Model
4.1 About this programmers model
4.2 V2M‑Juno r2 motherboard memory maps
4.2.1 Juno r2 SoC top‑level application and SMC interface memory maps
4.2.2 IOFPGA system peripherals memory map
4.2.3 DDR3L memory map
4.2.4 Additional Juno r2 SoC memory maps
4.3 APB system registers
4.3.1 APB system register summary
4.3.2 SYS_ID Register
4.3.3 SYS_SW Register
4.3.4 SYS_LED Register
4.3.5 SYS_100HZ Register
4.3.6 SYS_FLAG Registers
4.3.7 SYS_CFGSW Register
4.3.8 SYS_24MHZ Register
4.3.9 SYS_MISC Register
4.3.10 SYS_PCIE_CNTL Register
4.3.11 SYS_PCIE_GBE Register
4.3.12 SYS_PROC_ID0 Register
4.3.13 SYS_PROC_ID1 Register
4.3.14 SYS_FAN_SPEED Register
4.3.15 SP810_CTRL Register
4.4 APB system configuration registers
4.4.1 APB system configuration register summary
4.4.2 SYS_CFGDATA Register
4.4.3 SYS_CFGCTRL Register
4.4.4 SYS_CFGSTAT Register
4.5 APB energy meter registers
4.5.1 APB energy register summary
4.5.2 SYS_I_SYS Register
4.5.3 SYS_I_A72 Register
4.5.4 SYS_I_A53 Register
4.5.5 SYS_I_GPU Register
4.5.6 SYS_V_SYS Register
4.5.7 SYS_V_A72 Register
4.5.8 SYS_V_A53 Register
4.5.9 SYS_V_GPU Register
4.5.10 SYS_POW_SYS Register
4.5.11 SYS_POW_A72 Register
4.5.12 SYS_POW_A53 Register
4.5.13 SYS_POW_GPU Register
4.5.14 SYS_ENM_SYS Register
4.5.15 SYS_ENM_A72 Register
4.5.16 SYS_ENM_A53 Register
4.5.17 SYS_ENM_GPU Register
A Signal Descriptions
A.1 Debug connectors
A.1.1 P-JTAG connector
A.1.2 Trace connectors
A.2 Configuration 10Mbps Ethernet and dual‑USB connector
A.3 PCI Express Gigabit Ethernet and dual‑USB connector
A.4 SMC 10/100 Ethernet connector
A.5 Configuration USB connector
A.6 Header connectors
A.7 Keyboard and Mouse Interface (KMI) connector
A.8 HDMI connectors
A.9 PCI Express expansion slots
A.9.1 PCI Express ×4 connectors, one-lane slot 0 and slot 1
A.9.2 PCI Express ×8 connector, four-lane slot 2
A.9.3 PCI Express ×16 connector, four-lane slot 3
A.10 SATA 2.0 connectors
A.11 Dual‑UART connector
A.12 Secure keyboard and user push buttons connector
A.13 ATX power connector
B Specifications
B.1 Electrical specification
C Revisions
C.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0200-00 16 November 2015 Non-Confidential First issue of TRM
0200-01 15 July 2016 Non-Confidential Second issue of TRM
0200-02 10 January 2017 Non-Confidential Third issue of TRM
0200-03 10 April 2017 Non-Confidential Fourth issue of TRM
0200-04 20 April 2018 Non-Confidential Fifth issue of TRM

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Conformance Notices

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

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The system should be powered down when not in use.

It is recommended that ESD precautions are taken when handling Versatile™ Express boards.

The motherboard generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. There is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • Ensure attached cables do not lie across the target board
  • Reorient the receiving antenna
  • Increase the distance between the equipment and the receiver
  • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected
  • Consult the dealer or an experienced radio/TV technician for help


It is recommended that wherever possible shielded interface cables are used.
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