ARM® CoreSight™ ELA-500 Embedded Logic Analyzer Technical Reference Manual

Revision r2p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the ELA-500 Embedded Logic Analyzer
1.2 Definitions of terms used in this book
1.3 Compliance
1.4 Features
1.5 Interfaces
1.6 Configuration options
1.6.1 Configurable parameters
1.6.2 Static parameters
1.6.3 Tie-off signals
1.7 Test features
1.8 Product documentation and design flow
1.9 Product revisions
2 Functional description
2.1 About the functions
2.2 Interfaces
2.3 Clocking and reset
2.3.1 Clocking
2.3.2 Reset
2.4 Trace control and capture
2.4.1 Trace control
2.4.2 Trace capture
2.4.3 Second trace comparator on Trigger State 4
2.4.4 Trace SRAM format
2.4.5 Timestamp control
2.4.6 Debug APB registers and interface to SRAM
2.5 Triggering
2.5.1 Conditional trigger states
2.5.2 Transaction ID capture
2.6 Authentication interface
2.7 Parameter summary
3 Programmers model
3.1 Access permissions
3.2 Programming sequence
3.3 Control register summary
3.4 Control register descriptions
3.4.1 Logic Analyzer Control register
3.4.2 Timestamp Control register
3.4.3 Trigger State Select Register
3.4.4 Pre-trigger Action register
3.5 Current State register summary
3.6 Current State register descriptions
3.6.1 Current Trigger State Register
3.6.2 Current Counter Value Register
3.6.3 Current Action Value Register
3.6.4 Read Captured Transaction ID register
3.7 RAM register summary
3.8 RAM register descriptions
3.8.1 RAM Read Address Register
3.8.2 RAM Read Data Register
3.8.3 RAM Write Address Register
3.8.4 RAM Write Data Register
3.9 Trigger State register summary
3.10 Trigger State register descriptions
3.10.1 Signal Select registers
3.10.2 Trigger Control registers
3.10.3 Next State registers
3.10.4 Action registers
3.10.5 Alt Next State registers
3.10.6 Alt Action registers
3.10.7 Counter Compare registers
3.10.8 External Mask registers
3.10.9 External Compare registers
3.10.10 Signal Mask registers
3.10.11 Signal Compare registers
3.11 Integration Mode register summary
3.12 Integration Mode register descriptions
3.12.1 Integration Mode Action Trigger Output register
3.12.2 Integration Mode External Trigger Input register
3.12.3 Integration Mode Control register
3.13 Software Lock register summary
3.14 Software Lock register descriptions
3.14.1 Lock Access Register
3.14.2 Lock Status Register
3.15 Authentication register summary
3.16 Authentication register descriptions
3.16.1 Authentication Status register
3.17 Device register summary
3.18 Device register descriptions
3.18.1 Device Architecture register
3.18.2 Device Configuration register 2
3.18.3 Device Configuration register 1
3.18.4 Device Configuration register
3.18.5 Device Type Identifier register
3.19 ID register summary
3.20 ID register descriptions
3.20.1 Peripheral ID4 Register
3.20.2 Peripheral ID5 Register
3.20.3 Peripheral ID6 Register
3.20.4 Peripheral ID7 Register
3.20.5 Peripheral ID0 Register
3.20.6 Peripheral ID1 Register
3.20.7 Peripheral ID2 Register
3.20.8 Peripheral ID3 Register
3.20.9 Component ID0 Register
3.20.10 Component ID1 Register
3.20.11 Component ID2 Register
3.20.12 Component ID3 Register
A Signal descriptions
A.1 Clocks and reset
A.2 Debug APB signals
A.3 Observation interface signals
A.4 Timestamp interface signals
A.5 Authentication interface signals
A.6 DFT and MBIST interface signals
A.7 Q-Channel Low-Power interface signals
A.8 Output Action signals
A.9 External Trigger Input signals
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00-01 30 September 2014 Confidential First draft for r0p0 at BETA
0000-01 23 January 2015 Confidential First release for r0p0
0000-02 20 March 2015 Non-Confidential Second release for r0p0
0100-00 30 October 2015 Non-Confidential First release for r1p0
0200-00 23 May 2016 Non-Confidential First release for r2p0

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