ARM® Cortex®‑M3 Processor Technical Reference Manual

Revision r2p1

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1 Introduction
1.1 About the processor
1.2 Processor features list
1.3 External interfaces
1.4 Optional implementation components
1.5 Product documentation
1.5.1 Reference manuals
1.5.2 Design Flow
1.5.3 Architecture and protocol information
1.6 Product revisions
1.6.1 List of differences in functionality between r0p0 and r1p0
1.6.2 List of differences in functionality between r1p0 and r1p1
1.6.3 List of differences in functionality between r1p1 and r2p0
1.6.4 List of differences in functionality between r2p0 and r2p1
2 Functional Description
2.1 About the functions
2.2 Processor features list
2.3 Interfaces
2.3.1 Bus interfaces
2.3.2 ETM interface
2.3.3 AHB Trace Macrocell interface
2.3.4 Debug Port AHB-AP interface
3 Programmers Model
3.1 About the programmers’ model
3.2 Modes of operation and execution
3.3 Instruction set summary
3.3.1 Processor instructions
3.3.2 Load/store timings
3.3.3 Binary compatibility with other Cortex processors
3.4 Processor memory model
3.4.1 Memory regions table
3.4.2 Private Peripheral Bus
3.4.3 Unaligned accesses that cross regions
3.5 Write buffer
3.6 Exclusive monitor
3.7 Bit-banding
3.7.1 About bit-banding
3.7.2 Directly accessing an alias region
3.7.3 Directly accessing a bit-band region
3.8 Processor core register summary
3.9 Exceptions
3.9.1 Exception handling and prioritization
3.9.2 Interrupt latency
3.9.3 Base register update in LDM and STM operations
4 System Control
4.1 System control registers
4.2 Auxiliary Control Register, ACTLR
4.3 CPUID Base Register, CPUID
4.4 Auxiliary Fault Status Register, AFSR
5 Memory Protection Unit
5.1 About the MPU
5.2 MPU functional description
5.3 MPU programmers model table
6 Nested Vectored Interrupt Controller
6.1 NVIC functional description
6.1.1 NVIC interrupts
6.1.2 Low power modes
6.1.3 Level versus pulse interrupts
6.2 NVIC programmers’ model
6.2.1 Table of NVIC registers
6.2.2 Interrupt Controller Type Register, ICTR
7 Debug
7.1 Debug configuration
7.1.1 CoreSight™ discovery
7.1.2 Debugger actions for identifying the processor
7.1.3 ROM table identification and entries
7.1.4 ROM table components
7.1.5 System Control Space
7.1.6 Debug register summary
7.2 AHB-AP debug access port
7.2.1 AHB-AP transaction types
7.2.2 AHB-AP programmers model
7.3 Flash Patch and Breakpoint Unit (FPB)
7.3.1 FPB full and reduced units
7.3.2 FPB functional description
7.3.3 FPB programmers’ model
8 Data Watchpoint and Trace Unit
8.1 DWT functional description
8.2 DWT Programmers’ model
9 Instrumentation Trace Macrocell Unit
9.1 ITM functional description
9.2 ITM programmers’ model
9.3 ITM Trace Privilege Register, ITM_TPR
10 Embedded Trace Macrocell
10.1 About the ETM
10.1.1 ETM architecture
10.1.2 ETM features list
10.1.3 Configurable options list
10.2 ETM functional description
10.2.1 ETM block diagram
10.2.2 Low-bandwidth data tracing
10.2.3 Resources
10.2.4 Timestamp format
10.2.5 Periodic synchronization
10.2.6 Data and instruction address compare resources
10.2.7 External inputs
10.2.8 Start/stop block
10.2.9 Triggering
10.2.10 Interfaces
10.2.11 Operation
10.3 ETM Programmers model
10.3.1 Modes of operation and execution
10.3.2 ETM register summary table
10.3.3 Main Control Register, ETMCR
10.3.4 Configuration Code Register, ETMCCR
10.3.5 System Configuration Register, ETMSCR
10.3.6 TraceEnable Control 1 Register, ETMTECR1 characteristics
10.3.7 ID Register, ETMIDR characteristics
10.3.8 Configuration Code Extension Register, ETMCCER characteristics
10.3.9 TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR
10.3.10 Device Power-Down Status Register, ETMPDSR
10.3.11 Integration Test Miscellaneous Inputs, ITMISCIN
10.3.12 Integration Test Trigger Out, ITTRIGOUT
10.3.13 ETM Integration Test ATB Control 2, ETM_ITATBCTR2
10.3.14 ETM Integration Test ATB Control 0, ETM_ITATBCTR0
11 Trace Port Interface Unit
11.1 About the TPIU
11.2 TPIU functional description
11.2.1 TPIU block diagram
11.2.2 TPIU formatter
11.2.3 Serial Wire Output format
11.3 TPIU programmers model
11.3.1 Asynchronous Clock Prescaler Register, TPIU_ACPR
11.3.2 Formatter and Flush Status Register, TPIU_FFSR
11.3.3 Formatter and Flush Control Register, TPIU_FFCR
11.3.4 TRIGGER
11.3.5 Integration ETM Data
11.3.6 ITATBCTR2
11.3.7 Integration ITM Data
11.3.8 ITATBCTR0
11.3.9 Integration Mode Control, TPIU_ITCTRL
11.3.10 TPIU_DEVID
A Revisions
A.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
A 15 December 2005 Confidential First Release
B 13 January 2006 Non-Confidential Confidentiality status amended
C 10 May 2006 Non-Confidential First Release for r1p0
D 27 September 2006 Non-Confidential First Release for r1p1
E 13 June 2007 Non-Confidential Minor update with no technical changes
F 11 April 2008 Confidential Limited release for SC300 r0p0
G 26 June 2008 Non-Confidential First Release for r2p0
H 26 February 2010 Non-Confidential Second Release for r2p0
I 07 July 2010 Non-Confidential First Release for r2p1
0201-00 24 February 2015 Non-Confidential Document source updated to comply with DITA standards. Document number changed to 100165. DITA-XML.

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