ARM® Cortex®‑M4 Processor Technical Reference Manual

Revision r0p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the processor
1.2 Features
1.3 External interfaces
1.4 Configurable options
1.5 Product documentation
1.5.1 Reference manuals
1.5.2 Design Flow
1.5.3 Architecture and protocol information
1.6 Product revisions
2 Functional Description
2.1 About the functions
2.2 Processor features
2.3 Interfaces
2.3.1 Bus interfaces
2.3.2 ETM interface
2.3.3 AHB Trace Macrocell interface
2.3.4 Debug Port AHB-AP interface
3 Programmers’ Model
3.1 About the programmers’ model
3.2 Modes of operation and execution
3.3 Instruction set summary
3.3.1 Table of processor instructions
3.3.2 Table of processor DSP instructions
3.3.3 Load/store timings
3.3.4 Binary compatibility with other Cortex processors
3.4 Processor memory model
3.4.1 Memory regions table
3.4.2 Private Peripheral Bus
3.4.3 Unaligned accesses that cross regions
3.5 Write buffer
3.6 Exclusive monitor
3.7 Bit-banding
3.7.1 About bit-banding
3.7.2 Directly accessing an alias region
3.7.3 Directly accessing a bit-band region
3.8 Processor core register summary
3.9 Exceptions
3.9.1 Exception handling and prioritization
3.9.2 Interrupt latency
3.9.3 Base register update in LDM and STM operations
4 System Control
4.1 System control registers
4.2 Auxiliary Control Register, ACTLR
4.3 CPUID Base Register, CPUID
4.4 Auxiliary Fault Status Register, AFSR
5 Memory Protection Unit
5.1 About the MPU
5.2 MPU functional description
5.3 MPU programmers model table
6 Nested Vectored Interrupt Controller
6.1 NVIC functional description
6.1.1 NVIC interrupts
6.1.2 Low power modes
6.1.3 Level versus pulse interrupts
6.2 NVIC programmers’ model
6.2.1 Table of NVIC registers
6.2.2 Interrupt Controller Type Register, ICTR
7 Floating-Point Unit
7.1 About the FPU
7.2 FPU functional description
7.2.1 FPU views of the register bank
7.2.2 Modes of operation
7.2.3 FPU instruction set table
7.2.4 Compliance with the IEEE 754 standard
7.2.5 Complete implementation of the IEEE 754 standard
7.2.6 IEEE 754 standard implementation choices
7.2.7 Exceptions
7.3 FPU programmers’ model
7.3.1 Floating Point system registers
7.3.2 Enabling the FPU
8 Debug
8.1 Debug configuration
8.1.1 CoreSight™ discovery
8.1.2 Debugger actions for identifying the processor
8.1.3 ROM table identification and entries
8.1.4 ROM table components
8.1.5 System Control Space registers
8.1.6 Debug register summary
8.2 AHB-AP debug access port
8.2.1 AHB-AP transaction types
8.2.2 AHB-AP programmers model
8.3 Flash Patch and Breakpoint Unit (FPB)
8.3.1 FPB full and reduced units
8.3.2 FPB functional description
8.3.3 FPB programmers’ model
9 Data Watchpoint and Trace Unit
9.1 DWT functional description
9.2 DWT Programmers’ model
10 Instrumentation Trace Macrocell Unit
10.1 ITM functional description
10.2 ITM programmers’ model
10.3 ITM Trace Privilege Register, ITM_TPR
11 Trace Port Interface Unit
11.1 About the TPIU
11.2 TPIU functional description
11.2.1 TPIU block diagram
11.2.2 TPIU formatter
11.2.3 Serial Wire Output format
11.3 TPIU programmers’ model
11.3.1 TPIU registers
11.3.2 Asynchronous Clock Prescaler Register, TPIU_ACPR
11.3.3 Formatter and Flush Status Register, TPIU_FFSR
11.3.4 Formatter and Flush Control Register, TPIU_FFCR
11.3.5 TRIGGER
11.3.6 Integration ETM Data
11.3.7 ITATBCTR2
11.3.8 Integration ITM Data
11.3.9 ITATBCTR0
11.3.10 Integration Mode Control, TPIU_ITCTRL
11.3.11 TPIU_DEVID
11.3.12 TPIU_DEVTYPE
A Revisions
A.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
A 22 December 2009 Non-Confidential First release for r0p0
B 02 March 2010 Non-Confidential Second release for r0p0
C 29 June 2010 Non-Confidential First release for r0p1
D 11 June 2013 Non-Confidential Second release for r0p1
0001-00 23 February 2015 Non-Confidential Document source updated to comply with DITA standards. Document number changed to 100166 following conversion to DITA-XML.

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