Arm® CoreLink™ CMN-600 Coherent Mesh Network Technical Reference Manual

Revision r3p0

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
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1 Introduction
1.1 About CMN-600
1.2 Compliance
1.3 Features
1.3.1 R2 Features
1.3.2 R3 Features
1.3.3 CML Properties, Support, and Requirements
1.3.4 CCIX and CXS property support
1.4 Interfaces
1.5 Configurable options
1.5.1 System component selection
1.5.2 Mesh sizing and top-level configuration
1.5.3 Device placement and configuration
1.6 Test features
1.7 Product documentation and design flow
1.8 Product revisions
2 Functional Description
2.1 About the functions
2.1.1 Crosspoint
2.1.2 Request node I/O bridge
2.1.3 Fully coherent home node
2.1.4 Home node I/O bridge
2.1.5 SBSX
2.1.6 CXG
2.1.7 Configuration node
2.1.8 Power/Clock Control Block
2.1.9 System Address Map overview
2.1.10 Debug and Trace Controller
2.1.11 QoS regulator
2.1.12 Credited slices
2.1.13 Component Aggregation Layer
2.2 System configurations
2.3 CML system configurations
2.4 Node ID mapping
2.5 Discovery
2.5.1 Configuration address space organization
2.5.2 Configuration register node structure
2.5.3 Child pointers
2.5.4 Discovery tree structure
2.6 Addressing capabilities
2.7 Atomics
2.7.1 HN-F
2.7.2 SN
2.7.3 HN-I
2.7.4 RN-I
2.8 Exclusive accesses
2.8.1 HN-F
2.8.2 HN-I
2.8.3 CML Exclusive Support
2.8.4 RN-I, RN-D
2.9 Processor events
2.10 Quality of Service
2.10.1 Architectural QoS support
2.10.2 Microarchitectural QoS support
2.10.3 QoS configuration
2.11 Barriers
2.12 DVM messages
2.13 PCIe integration
2.13.1 CMN-600 PCIe master and slave restrictions and requirements
2.13.2 CMN-600 System requirements
2.13.3 RN-I and HN-I programming sequence
2.14 Error handling
2.14.1 Error types
2.14.2 Error detection and deferred error values
2.14.3 Error detection, signaling, and reporting
2.14.4 Error handling requirements
2.14.5 HN-F error handling
2.14.6 HN-I error handling
2.14.7 SBSX error handling
2.14.8 RN-I error handling
2.14.9 XP error handling
2.14.10 CXHA error handling
2.14.11 CCIX PER messaging support
2.15 System Address Map
2.16 RN SAM
2.16.1 Target IDs
2.16.2 Memory region requirements
2.16.3 System Cache Groups
2.16.4 PrefetchTgt RN SAM
2.18 HN-F SAM
2.18.1 3 SN-F and 6 SN-F memory striping
2.18.2 SN contiguous address spaces
2.19 RN and HN-F SAM programming
2.19.1 SAM programming sequence
2.19.2 Region size configuration
2.19.3 Example memory map programming
2.19.4 Support for CCIX Port Aggregation
2.20 RN and HN-F SAM R2 Support
2.21 RN and HN-F SAM R3 Support
2.22 HN-I SAM
2.22.1 Sample system configuration
2.23 Cross chip routing and ID mapping
2.24 CMN-600 R3 128 RN-F support
2.25 CCIX Port Aggregation groups
2.26 GIC communication over AXI4 Stream ports
2.27 Clocking
2.27.1 Clock domains
2.27.2 CML clock inputs
2.27.3 Clock hierarchy
2.27.4 Global clock
2.27.5 Clock enable inputs
2.27.6 Timing closure with credited slices
2.28 Reset
2.28.1 CML reset
2.29 Power and clock management
2.29.1 High-level clock gating (HCG)
2.29.2 Power domains
2.29.3 Power domain control
2.29.4 P-Channel on device reset
2.29.5 CXS power domain
2.29.6 HNF memory retention
2.29.7 HN-F power domains
2.29.8 HN-F RAM PCSM Interface
2.29.9 SLC data RAM retention control
2.29.10 HN-F power domain completion interrupt
2.30 RN entry to and exit from Snoop and DVM domains
2.30.1 Hardware interface
2.30.2 Software interface
2.31 Link layer
2.31.1 Flit buffer sizing requirements
2.32 CML Symmetric Multi-Processor (SMP) Support
3 Programmers Model
3.1 About the programmers model
3.1.1 Node configuration register address mapping
3.1.2 Global configuration register region
3.1.3 XP configuration register region
3.1.4 Component configuration register region
3.1.5 Requirements of configuration register reads and writes
3.2 Register summary
3.2.1 Configuration master register summary
3.2.2 DN register summary
3.2.3 Debug and trace register summary
3.2.4 HN-F register summary
3.2.5 HN-I register summary
3.2.6 XP register summary
3.2.7 RN-D register summary
3.2.8 RN-I register summary
3.2.9 RN SAM register summary
3.2.10 SBSX register summary
3.2.11 CXHA register summary
3.2.12 CXRA register summary
3.2.13 CXLA register summary
3.3 Register descriptions
3.3.1 Configuration master register descriptions
3.3.2 DN register descriptions
3.3.3 Debug and trace register descriptions
3.3.4 HN-F register descriptions
3.3.5 HN-I register descriptions
3.3.6 XP register descriptions
3.3.7 RN-D register descriptions
3.3.8 RN-I register descriptions
3.3.9 RN SAM register descriptions
3.3.10 SBSX register descriptions
3.3.11 CXHA configuration registers
3.3.12 CXRA configuration registers
3.3.13 CXLA configuration registers
3.4 CMN-600 programming
3.4.1 Boot-time programming requirements
3.4.2 Runtime programming requirements
3.5 CML programming
3.5.1 CMN-600 CML (CCIX) Related Programmable Registers
3.5.2 CML Bring-up Sequence
3.5.3 CMN-600 initial programming requirements to enable CCIX communication
3.5.4 Runtime programming
3.5.5 CCIX Protocol Link-up Sequence
3.5.6 CCIX Protocol Link-down Sequence
3.5.7 CCIX Protocol Link Coherency and DVM Domain Entry/Exit
3.6 Support for RN-Fs compliant with CHI Issue A specification
3.6.1 CHI Issue A device node ID mapping
3.6.2 Stashing
3.6.3 Direct Cache Transfer
3.6.4 Data poison
3.6.5 RN SAM programming
3.6.6 System coherency entry and exit
4 SLC Memory System
4.1 About the SLC memory system
4.2 Configurable options
4.3 Basic operation
4.4 Cache maintenance operations
4.5 Cacheable and Non-cacheable exclusives
4.6 TrustZone technology support
4.7 Snoop connectivity and control
4.8 QoS features
4.8.1 QoS decoding
4.8.2 QoS class and POCQ resource availability
4.9 CMN-600 Hardware-based cache flush engine
4.10 Data Source Handling
4.11 Software configurable memory region locking
4.12 Software-configurable On-Chip Memory
4.13 CMO propagation from HN-F to SN-F/SBSX
4.14 Source-based SLC cache partitioning
4.15 Way-based SLC cache partitioning
4.16 Error reporting and software-configured error injection
4.16.1 Software-configurable error injection
4.16.2 Software-configurable parity error injection
5 Debug trace and PMU
5.1 DT system overview
5.1.1 DTM watchpoint
5.1.2 DTM FIFO buffer
5.1.3 Read mode
5.1.4 DTC
5.1.5 ATB packets
5.2 DT programming
5.2.1 DTM watchpoint programming
5.2.2 DTC programming
5.3 DT usage examples
5.3.1 Flit tracing
5.3.2 Trace tag
5.3.3 Debug watch trigger
5.3.4 Cross trigger
5.4 PMU system overview
5.5 PMU feature description
5.6 PMU system programming
5.6.1 PMU counter setup
5.6.2 PMU snapshot programming
5.6.3 PMU interrupt programming
5.7 Secure debug support
6 Performance Optimization and Monitoring
6.1 Performance optimization guidelines
6.2 About the Performance Monitoring Unit
6.2.1 Cycle counter
6.3 HN-F performance events
6.3.1 Cache performance
6.3.2 HN-F counters
6.3.3 SF events
6.3.4 System-wide events
6.3.5 Quality of Service
6.3.6 HN-F PMU event summary
6.4 RN-I performance events
6.4.1 Bandwidth at RN-I bridges
6.4.2 Bottleneck analysis at RN-I bridges
6.4.3 RN-I PMU event summary
6.5 SBSX performance events
6.5.1 Bandwidth at SBSX bridges
6.5.2 Bottleneck analysis at SBSX bridges
6.5.3 SBSX PMU event summary
6.6 HN-I performance events
6.6.1 Bandwidth at HN-I bridges
6.6.2 Bottleneck analysis at HN-I bridges
6.6.3 HN-I PMU event summary
6.7 DN performance events
6.8 XP PMU event summary
6.9 Occupancy and lifetime measurement using PMU events
6.10 DEVEVENT in CMN-600
A Signal Descriptions
A.1 About the signal descriptions
A.2 Clock and reset signals
A.3 Clock management signals
A.4 Power management signals
A.5 Interrupt and event signals
A.6 Configuration input signals
A.7 Device population signals
A.8 CHI interface signals
A.8.1 Per-device interface definition
A.8.2 Per-channel interface signals
A.8.3 Non-channel-specific interface signals
A.9 ACE-Lite and AXI Interface signals
A.9.1 ACE-Lite-with-DVM slave interface signals
A.9.2 AXI/ACE-Lite master interface signals
A.9.3 A4S Signal list
A.10 CXLA interface signals
A.11 Debug, trace, and PMU interface signals
A.12 DFT and MBIST interface signals
A.13 RN SAM configuration interface signals
A.14 Processor event interface signals
B CXS Specification
B.1 CCIX interfaces
B.1.1 CXS basic operation
B.1.2 CXS interface attributes
B.2 Signal descriptions
B.3 Packet control fields
B.4 Packet size constraints
B.5 Packet position constraints
B.6 CCIX Packet Details
B.7 Packet examples
B.8 CXS flow control
B.9 CXS interface activation and deactivation
B.9.1 Request and acknowledge handshaking
B.9.2 Race conditions
B.9.3 Response to a new state
B.9.4 Interface activation and deactivation examples
B.10 CXS packet continuous delivery guarantees
B.11 CXS Error signaling
B.11.1 Transport errors
B.11.2 Packet errors
B.11.3 Errors outside of CXS scope
C Revisions
C.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 12 February 2016 Non-Confidential First release of r0p0
0000-01 21 October 2016 Non-Confidential Second release of r0p0
0101-00 31 March 2017 Non-Confidential First DEV release of r1p1
0100-00 23 June 2017 Non-Confidential First EAC release of r1p0
0101-00 31 August 2017 Non-Confidential First EAC release of r1p1
0102-00 18 November 2017 Non-Confidential First EAC release of r1p2
0103-00 08 February 2018 Non-Confidential First EAC release of r1p3
0103-01 02 March 2018 Non-Confidential Second EAC release of r1p3
0200-00 22 May 2018 Non-Confidential First EAC release of r2p0
0300-00 03 August 2018 Non-Confidential First EAC release of r3p0

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