ARM® Cortex®‑M33 Processor Technical Reference Manual

Revision r0p2


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Typographic conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
Part A Introduction
A1 Introduction
A1.1 About the processor
A1.2 Processor features
A1.3 Processor configuration options
A1.4 Component blocks
A1.4.1 Processor core
A1.4.2 Security attribution and memory protection
A1.4.3 Floating-Point Unit
A1.4.4 Nested Vectored Interrupt Controller
A1.4.5 Cross Trigger Interface Unit
A1.4.6 ETM
A1.4.7 MTB
A1.4.8 Debug and trace
A1.5 Interfaces
A1.6 Compliance
A1.7 Design process
A1.8 Documentation
A1.9 Product revisions
Part B Functional description
B1 Programmers Model
B1.1 About the programmers model
B1.2 Modes of operation and execution
B1.3 Instruction set summary
B1.4 Memory model
B1.4.1 Private Peripheral Bus
B1.4.2 Unaligned accesses
B1.5 Exclusive monitor
B1.6 Processor core registers summary
B1.7 Exceptions
B1.7.1 Exception handling and prioritization
B2 System Control
B2.1 Identification register summary
B2.2 Auxiliary Control Register
B2.3 CPUID Base Register
B3 Security Attribution and Memory Protection
B3.1 About Security Attribution and Memory Protection
B3.2 SAU register summary
B3.3 MPU register summary
B4 Nested Vectored Interrupt Controller
B4.1 NVIC programmers model
B4.1.1 NVIC register summary
B4.1.2 Interrupt Controller Type Register
B5 Floating-Point Unit
B5.1 About the FPU
B5.2 FPU functional description
B5.2.1 FPU views of the register bank
B5.2.2 Modes of operation
B5.2.3 Compliance with the IEEE 754 standard
B5.2.4 Exceptions
B5.3 FPU programmers model
B5.3.1 Floating-point system registers
B5.3.2 Low-power operation
B6 External coprocessors
B6.1 About external coprocessors
B6.2 Operation
B6.3 Usage restrictions
B6.4 Data transfer rates
B6.5 Configuring which coprocessors are included in Secure and Non-secure states
B6.6 Debug access to coprocessor registers usage constraints
B6.7 Exceptions and context switch
Part C Debug and trace components
C1 Debug
C1.1 Debug functionality
C1.1.1 CoreSight™ discovery
C1.1.2 Debugger actions for identifying the processor
C1.1.3 Processor ROM table identification and entries
C1.1.4 System Control Space registers
C1.1.5 Debug register summary
C1.2 About the D-AHB interface
C2 Instrumentation Trace Macrocell Unit
C2.1 ITM programmers model
C2.1.1 ITM register summary table
C2.1.2 ITM Trace Privilege Register
C2.1.3 ITM Integration Mode Control Register
C2.1.4 Integration Mode Write ATB Valid Register
C2.1.5 Integration Mode Read ATB Ready Register
C3 Data Watchpoint and Trace Unit
C3.1 DWT functional description
C3.2 DWT programmers model
C4 Cross Trigger Interface
C4.1 About the Cross Trigger Interface
C4.2 CTI functional description
C4.3 CTI programmers model
C5 Breakpoint Unit
C5.1 About the Breakpoint Unit
C5.2 BPU programmers model
C5.3 BPU functional description
Part D Appendices
A Debug Access Port
A.1 About the Debug Access Port
A.1.1 Configuration options
A.2 Functional description
A.3 DAP register summary
A.3.1 AHB-AP register summary
A.3.2 Debug port register summary
A.4 DAP register descriptions
A.4.1 AHB-AP register descriptions
A.4.2 Debug port registers
B Trace Port Interface Unit
B.1 About the TPIU
B.2 TPIU functional description
B.2.1 TPIU Formatter
B.2.2 Serial Wire Output format
B.3 TPIU programmers model
B.3.1 Asynchronous Clock Prescaler Register
B.3.2 Formatter and Flush Status Register
B.3.3 Formatter and Flush Control Register
B.3.4 TRIGGER Register
B.3.5 Integration Test FIFO Test Data 0 Register
B.3.6 Integration Test ATB Control Register 2
B.3.7 Integration Test FIFO Test Data 1 Register
B.3.8 Integration Test ATB Control 0 Register
B.3.9 Integration Mode Control
B.3.10 Device Configuration Register
B.3.11 Device Type Identifier Register
C UNPREDICTABLE Behaviors
C.1 Use of instructions defined in architecture variants
C.2 Use of Program Counter - R15 encoding
C.3 Use of Stack Pointer - as a general purpose register R13
C.4 Register list in load and store multiple instructions
C.5 Exception-continuable instructions
C.6 Stack limit checking
C.7 UNPREDICTABLE instructions within an IT block
C.8 Memory access and address space
C.9 Load exclusive and Store exclusive accesses
C.10 ARMv8-M MPU programming
C.11 Miscellaneous UNPREDICTABLE instruction behavior
D Revisions
D.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 28 September 2016 Confidential First release for r0p0
0001-00 03 February 2017 Confidential First release for r0p1
0002-00 10 May 2017 Non-Confidential First release for r0p2

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