Arm Cortex‑M33 Processor Technical Reference Manual : C1.1.4 System Control Space registers

C1.1.4 System Control Space registers

The processor provides debug through registers in the System Control Space (SCS).

SCS CoreSight™ identification

The following table shows the SCS CoreSight™ identification registers and values for debugger detection. Final debugger identification of the Cortex^®‑M33 processor is through the CPUID register in the SCS.

Table C1-3 SCS identification values

Address offset	Register name	Reset value	Description
`0xE000EFD0`	SCS_PIDR4	`0x00000004`	Component and Peripheral ID register formats in the Armv8‑M Architecture Reference Manual
`0xE000EFD4`	SCS_PIDR5	`0x00000000`
`0xE000EFD8`	SCS_PIDR6	`0x00000000`
`0xE000EFDC`	SCS_PIDR7	`0x00000000`
`0xE000EFE0`	SCS_PIDR0	`0x00000021`
`0xE000EFE4`	SCS_PIDR1	`0x000000BD`
`0xE000EFE8`	SCS_PIDR2	`0x0000000B`
`0xE000EFEC`	SCS_PIDR3	`0x00000000`^a
`0xE000EFF0`	SCS_CIDR0	`0x0000000D`
`0xE000EFF4`	SCS_CIDR1	`0x00000090`
`0xE000EFF8`	SCS_CIDR2	`0x00000005`
`0xE000EFFC`	SCS_CIDR3	`0x000000B1`
`0xE000EFBC`	SCS_DEVARCH	`0x47702A04`

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