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Home > Debug and trace components > Debug > Debug functionality > System Control Space registers |
The processor provides debug through registers in the System Control Space (SCS).
The following table shows the SCS CoreSight™ identification registers and values for debugger detection. Final debugger identification of the Cortex®‑M33 processor is through the CPUID register in the SCS.
Table C1-3 SCS identification values
Address offset | Register name | Reset value | Description |
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SCS_PIDR4 |
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Component and Peripheral ID register formats in the Armv8‑M Architecture Reference Manual |
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SCS_PIDR5 |
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SCS_PIDR6 |
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SCS_PIDR7 |
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SCS_PIDR0 |
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SCS_PIDR1 |
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SCS_PIDR2 |
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SCS_PIDR3 | a |
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SCS_CIDR0 |
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SCS_CIDR1 |
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SCS_CIDR2 |
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SCS_CIDR3 |
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SCS_DEVARCH |
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