A.4.1 AHB-AP register descriptions

This section describes the programmable AHB-AP registers. It contains the following registers:

AHB-AP Control/Status Word register, CSW, 0x00

AHB-AP Control/Status Word register configures and controls transfers through the AHB interface.

Attributes
See A.3 DAP register summary.

The following figure shows the AHB-AP CSW register bit assignments.

Figure A-3 AHB-AP CSW register bit assignments
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The following table shows the AHB-AP CSW register bit assignments.

Table A-4 AHB-AP Control/Status Word register bit assignments

Bits Type Name Function
[31] RO DbgSwEnable

Not implemented in Cortex®‑M33 DAP. Treat as RAZ/SBZP.

[30] RW Prot Specifies the security of the AHB transfer output on SLVNONSEC.
0Secure transfer.
1Non-secure transfer.
This bit resets to 0.
[29:28] RW - Reserved, SBZ.
[27:24] RW Prot

Specifies the signal encodings to be output on SLVPROT[6], SLVPROT[4], and SLVPROT[3:0].

SLVPROT[6]CSW.Prot[27]
SLVPROT[4]CSW.Prot[27]
SLVPROT[3:0]CSW.Prot[27:24]

Note:

  • CSW.Prot[27] is tied to 0.
  • SLVPROT[5] is tied to 0.
[23] RO SPIDEN Not implemented in Cortex‑M33 DAP. Treat as RAZ/SBZP.
[22:12] - - Reserved. Treat as RAZ/SBZP.
[11:8] RO Mode

Not implemented in Cortex‑M33 DAP. Treat as RAZ/SBZP.

[7] RO TrInProg

Not implemented in Cortex‑M33 DAP. Treat as RAZ/SBZP.

[6] RO DbgStatus

Indicates the status of the DEVICEEN port. If DbgStatus is LOW, no AHB transfers are carried out.

0AHB transfers not permitted.
1AHB transfers permitted.
[5:4] RW AddrInc

Auto address increment and packing mode on RW data access. Only increments if the current transaction completes without an error response and the transaction is not aborted.

Auto address incrementing and packed transfers are not performed on access to Banked Data registers, 0x10-0x1C. The status of these bits is ignored in these cases.

Incrementing and wrapping is performed within a 1KB address boundary, for example, for word incrementing from 0x1400-0x17FC. If the start is at 0x14A0, then the counter increments to 0x17FC, wraps to 0x1400, then continues incrementing to 0x149C.

0b00Auto increment OFF.
0b01Increment, single.

Single transfer from corresponding byte lane.

0b10Reserved, SBZ. No transfer.
0b11Reserved, SBZ. No transfer.

The Size field, bits[2:0] defines the size of address increment

The reset value is 0b00.

Note:

Bit[5] is RO and RAZ.
[3] RW -

Reserved, SBZ.

The reset value is 0.

[2:0] RW Size

Size of the data access to perform:

0b0008 bits.
0b00116 bits.
0b01032 bits.
0b011-0b111Reserved, SBZ.

The reset value is 0b000.

Note:

Bit[2] is RO and RAZ.
Prot field bit descriptions

The following table describes Prot field bits.

Table A-5 Prot field bit descriptions

Bit Description
27

Shareable, Lookup, Modifiable:

0Non-shareable, no-look up, non-modifiable.
1Shareable, lookup, modifiable.
26

Bufferable:

0Non-bufferable.
1Bufferable.
25

Privileged:

0Non-privileged.
1Privileged.
24

Data/Instruction access:

1Data access. This bit is RO.

AHB-AP Transfer Address Register, TAR, 0x04

AHB-AP Transfer Address Register holds the memory address to be accessed.

Attributes
See A.3 DAP register summary.

The following table shows the AHB-AP Transfer Address Register bit assignments.

Table A-6 AHB-AP Transfer Address Register bit assignments

Bits Type Name Function
[31:0] RW Address

Address of the current transfer

Note:

This register is not reset

AHB-AP Data Read/Write register, DRW, 0x0C

AHB-AP Data Read/Write register maps an AP access directly to one or more memory accesses. The AP access does not complete until the memory access, or accesses, complete.

Attributes
See A.3 DAP register summary.

The following table shows the AHB-AP Data Read/Write register bit assignments.

Table A-7 AHB-AP Data Read/Write register bit assignments

Bits Type Name Function
[31:0] RW Data
Write mode
Data value to write for the current transfer.
Read mode
Data value that is read from the current transfer.

AHB-AP Banked Data registers, BD0-BD03, 0x10-0x1C

AHB-AP Banked Data registers, BD0-BD03 provide a mechanism for directly mapping through DAP accesses to AHB transfers without having to rewrite the TAR within a four-location boundary. BD0 is RW from TA. BD1 is RW from TA+4.

Attributes
See A.3 DAP register summary.

The following table shows the Banked Data register bit assignments.

Table A-8 Banked Data register bit assignments

Bits Type Name Function
[31:0] RW Data

If dapcaddr[7:4] = 0x0001, it is accessing AHB-AP registers in the range 0x10-0x1C, and the derived haddr[31:0] is:

Write mode
Data value to write for the current transfer to external address TAR[31:4] + dapcaddr[3:2] + 0b00.
Read mode
Data value that is read from the current transfer from external address TAR[31:4] + dapcaddr[3:2] + 0b00.

Auto address incrementing is not performed on DAP accesses to BD0-BD3.

Banked transfers are only supported for word transfers. Non-word banked transfers are reserved and unpredictable. Transfer size is ignored for banked transfers.

AHB-AP Debug Base Address register, ROM, 0xF8

AHB-AP Debug Base Address register provides an index into the connected memory-mapped resource. This index value points to a ROM table that describes the connected debug components.

Attributes
See A.3 DAP register summary.

The following table shows the AHB-AP Debug Base Address register bit assignments.

Table A-9 AHB-AP Debug Base Address register bit assignments

Bits Type Name Function
[31:0] RO Debug AHB ROM Address

Base address of a ROM table. Bit[1] is always 1, bits[31:12] are set to the tie-off value on the static input port BASEADDR[31:12]. Bits[11:2] are set to 0x000 and bit[0] is set to BASEADDR[0].

The ROM provides a lookup table that points to debug components.

AHB-AP Configuration register, CFG, 0xF4

AHB-AP configuration register describes the features that are configured in the AHB-AP implementation.

Attributes
See A.3 DAP register summary.

The following table shows the AHB-AP Configuration register bit assignments.

Table A-10 AHB-AP Configuration register bit assignments

Bits Type Name Value Function
[31:3] - Reserved 0x00000000 -
[2] RO LD 0x0 Large data. Data not larger than 32-bits supported.
[1] RO LA 0x0 Long address. Physical addresses of 32 bits, or less supported. Greater than 32 bits is not supported.
[0] RO BE 0x0 Only little-endian supported.

AHB-AP Identification Register, IDR, 0xFC

AHB-AP Identification register specifies the AHB-AP identification values.

The following figure shows the AHB-AP Identification Register bit assignments.

Figure A-4 AHB-AP Identification Register bit assignments
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The following table shows the AHB-AP Identification Register bit assignments.

Table A-11 AHB-AP Identification Register bit assignments

Bits Type Name Value Function
[31:28] RO Revision 0x1 r0p1
[27:24] RO JEDEC bank 0x4 Designed by Arm®
[23:17] RO JEDEC code 0x3B Designed by Arm
[16:13] RO Class 0x8 Is a Mem AP
[12:8] - Reserved 0x00 -
[7:4] RO Variant 0x1 Cortex‑M33
[3:0] RO Type 0x5 AHB5
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