A.4.2 Debug port registers

This section describes the DP registers.

AP Abort register, ABORT

AP Abort register forces an AP transaction abort.

Attributes
The ABORT register is:
  • A write-only register.
  • Accessible through JTAG-DP and SW-DP.
  • Accessed in a data link defined manner:

    • JTAG-DP access is through its own scan-chain.

    • A write to offset 0x0 of the DP register map accesses SW-DP.
  • Always accessible, completes all accesses on the first attempt, and returns an OK response if a valid transaction is received.

The following figure shows the ABORT bit assignments.

Figure A-5 ABORT bit assignments
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The following table shows the ABORT bit assignments.

Table A-12 ABORT bit assignments

Bits Function Description
[31:5] - Reserved, SBZ.
[4] ORUNERRCLR Setting this bit to 1 sets the STICKYORUN overrun error flagb to 0.
[3] WDERRCLRa Setting this bit to 1 sets the WDATAERR write data error flagb to 0.
[2] STKERRCLR Setting this bit to 1 sets the STICKYERR sticky error flagb to 0.
[1] STKCMPCLR Reserved, SBZ. The DP is a MINDP implementation, therefore this bit is not implemented.
[0] DAPABORT

Setting this bit to 1 generates a DAP abort, that aborts the current AP transaction.

Note:

Perform this only if the debugger has received WAIT responses over an extended period.

Identification Code register, IDCODE

Identification Code register provides identification information about the JTAG-DP. The IDCODE register is always accessible.

Attributes
The IDCODE register is:
  • A read-only register.
  • Accessed through its own scan chain when the IR contains 0b1110.

The following figure shows the Identification Code register bit assignments.

Figure A-6 Identification Code register bit assignments
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The following table shows the Identification Code register bit assignments.

Table A-13 Identification Code register bit assignments

Bits Function Description
[31:28] Version

Cortex®‑M33 JTAG-DP revision code exclusive OR-gated with ECOREVNUM[7:4] signal:

0x0r0p0.
[27:12] PARTNO

Part Number for the Cortex‑M33 JTAG-DP, 0xBA04.

[11:1] MANUFACTURER

JEDEC Manufacturer ID, an 11-bit JEDEC code that identifies the designer of the device. See JEDEC Manufacturer ID. in this figure shows the Arm value for this field as 0x23B. This value must not be changed.

[0] - Always 1.
JEDEC Manufacturer ID

This code is also described as the JEP-106 manufacturer identification code, and can be subdivided into two fields, as the following table shows. The JEDEC Solid-State Technology Association assign JEDEC codes.

See the JEDEC Standard Manufacturer’s Identification Code, JEP106.

Table A-14 JEDEC JEP106 manufacturer ID code, with Arm® values

MANUFACTURER field Bitsc Arm registered value
Continuation code 4 bits, [11:8] 0b0100, 0x4
Identity code 7 bits, [7:1] 0b0111011, 0x3B

Debug Port Identification Register, DPIDR

Debug Port Identification register provides identification information about the JTAG-DP and SW-DP.

Attributes
The DPIDR register is:
  • A read-only register.
  • Accessed by a read at offset 0x0 of the DP register map.

The following figure shows the Debug Port Identification Register bit assignments.

Figure A-7 Debug Port Identification Register bit assignments
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The following table shows Debug Port Identification Register the bit assignments.

Table A-15 Debug Port Identification Register bit assignments

Bits Function Description
[31:28] REVISION

Cortex‑M33 DP revision code exclusive OR-gated with the ECOREVNUM[7:4] signal:

JTAG-DP
0x0, r0p0.
SW-DP
0x0, r0p0.
[27:20] PARTNO

Part Number for this debug port, 0xBE.

[19:17] - Reserved, RAZ.
[16] MIN

Reads as 1, indicating that the Minimal Debug Port (MINDP) architecture is implemented.

Transaction counter, Pushed-verify, and Pushed-find operations are not implemented.

[15:12] VERSION

JTAG-DP is DP architecture version is 0x1.

SW-DP is DP architecture version is 0x2.

[11:1] MANUFACTURER

JEDEC Manufacturer ID, an 11-bit JEDEC code that identifies the designer of the device. See JEDEC Manufacturer ID. Identification Code register bit assignments shows the Arm value for this field as 0x23B. This value must not be changed.

[0] - Always 1.

Control/Status register, CTRL/STAT

Control/Status register provides control of the DP and its status information.

Attributes

The CTRL/STAT register is:

  • A read/write register. Some fields are RO, meaning they ignore writes, see the field descriptions for more information.
  • JTAG-DP. At address 0x4 when the IR contains DPACC, when SELECT.DPBANKSEL is 0x0.
  • SW-DP. At address 0x4 when APnDP bit is 0, and SELECT.DPBANKSEL is 0x0.

The following figure shows the Control/Status register bit assignments.

Figure A-8 Control/Status register bit assignments
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The following table shows the Control/Status register bit assignments.

Table A-16 Control/Status register bit assignments

Bits Access Function Description
[31] RO CSYSPWRUPACK System powerup acknowledge.
[30] RW CSYSPWRUPREQ

System powerup request.

The reset value is 0.

[29] RO CDBGPWRUPACK Debug powerup acknowledge.
[28] RW CDBGPWRUPREQ

Debug powerup request.

The reset value is 0.

[27] RO CDBGRSTACK Debug reset acknowledge.
[26] RW CDBGRSTREQ

Debug reset request.

The reset value is 0.

[25:24] - - Reserved, RAZ/SBZP.
[23:12] RAZ/ SBZP TRNCNT

The Cortex‑M33 is a MINDP implementation, therefore this field is reserved.

[11:8] RAZ/ SBZP MASKLANE

The Cortex‑M33 is a MINDP implementation, therefore this field is reserved.

[7] ROd WDATAERRe

If a Write Data Error occurs, this bit is set to 1. It is set if:

  • There is a parity or framing error on the data phase of a write.
  • A write that the debug port accepted is then discarded without being submitted to the access port.

This bit can only be set to 0 by writing 1 to ABORT.WDERRCLR.

The reset value after a Powerup reset is 0.

[6] ROd READOKe

If the response to the previous access port read or RDBUFF read was OK, this bit is set to 1. If the response was not OK, it is set to 0.

This flag always indicates the response to the last access port read access.

The reset value after a Powerup reset is 0.

[5] ROd STICKYERR

If an error is returned by an access port transaction, this bit is set to 1. To set this bit to 0:

JTAG-DP

Either:

  • Write 1 to this bit of this register.
  • Write 1 to ABORT.STKERRCLR.
SW-DP
Write 1 to ABORT.STKERRCLR.

After a Powerup reset, this bit is LOW.

[4] RAZ STICKYCMP

The Cortex‑M33 is a MINDP implementation, therefore this field is reserved.

[3:2] RAZ/ SBZP TRNMODE

The Cortex‑M33 is a MINDP implementation, therefore this field is reserved.

[1] ROd STICKYORUN

If overrun detection is enabled (see bit[0] of this register), this bit is set to 1 when an overrun occurs. To set this bit to 0:

JTAG-DP

Either:

  • Write 1 to this bit of this register.
  • Write 1 to ABORT.ORUNERRCLR.
SW-DP
Write 1 to ABORT.ORUNERRCLR.

After a Powerup reset, the reset value is 0.

[0] RW ORUNDETECT

This bit is set to 1 to enable overrun detection.

The reset value is 0.

AP Select register, SELECT

The AP Select register selects, an Access Port (AP) and the active register banks within that AP, and the DP address bank.

Attributes

The SELECT register is:

  • A write-only register.
  • JTAG-DP. At address 0x8 when the IR contains DPACC, and is a WO register.
  • SW-DP. At address 0x8 on write operations, when the APnDP bit is 0.

The following figure shows the AP Select register bit assignments.

Figure A-9 AP Select register bit assignments
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The following table shows the AP Select register bit assignments.

Table A-17 AP Select register bit assignments

Bits Function Description
[31:24] APSEL

Selects the current access port:

0x00

Selects the AHB-AP.

0x01-0x1F
AP 0x01-0x1F do not exist, and if selected, AP read transactions return zero and AP writes are ignored.

The reset value is unpredictable.

[23:8] Reserved. SBZ/RAZ Reserved. SBZ/RAZ.
[7:4] APBANKSEL

Selects the active 4-word register window on the current access port.

The reset value is unpredictable.

[3:0] DPBANKSEL

Selects the register that appears at DP register 0x4.

JTAG-DP register allocation:

0x0CTRL/STAT.

SW-DP register allocation in DPv1:

0x0CTRL/STAT.
0x1DLCR.

SW-DP register allocation in DPv2:

0x0CTRL/STAT.
0x1DLCR.
0x2TARGETID.
0x3DLPIDR.
0x4EVENTSTAT.

Read Buffer register, RDBUFF

Read Buffer register captures data from the AP that is presented as the result of a previous read.

Attributes

The RDBUFF register is:

Read Buffer implementation and use on a JTAG-DP

On a JTAG-DP, the read buffer is RAZ/WI.

The read buffer is architecturally defined to provide a debug port read operation that does not have any side effects. This means that a debugger can insert a debug port read of the read buffer at the end of a sequence of operations to return the final AP read result and ACK values.

Read Buffer implementation and use on an SW-DP

On an SW-DP, performing a read of the read buffer captures data from the access port, presented as the result of a previous read, without initiating a new access port transaction. This means that reading the read buffer returns the result of the last access port read access, without generating a new AP access.

After you read the read buffer, its contents are no longer valid. The result of a second read of the read buffer is unpredictable.

If you require the value from an access port register read, that read must be followed by one of:

  • A second access port register read. You can read the CSW if you want to ensure that this second read has no side effects.
  • A read of the DP Read Buffer.

This second access, to the access port or the debug port depending on which option you use, stalls until the result of the original access port read is available.

Event Status register, EVENTSTAT

Event Status register signals to the debugger that the Cortex®‑M33 processor is halted.

Attributes

The EVENTSTAT register is:

  • A read-only register.
  • Accessed by a read at offset 0x4 of the DP register map when SELECT.DPBANKSEL is set to 0x4.

The following figure shows the Event Status register bit assignments.

Figure A-10 Event Status register bit assignments
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The following table shows the Event Status register bit assignments.

Table A-18 Event Status register bit assignments

Bits Function Description
[31:1] - Reserved, RAZ.
[0] EA

Event status flag. Indicates that the Cortex‑M33 processor is halted:

0

Processor is halted.

1
Processor is not halted.

Data Link Control Register, DLCR (SW-DP only)

Data Link Control register controls the operating mode of the Data Link.

Attributes

The DLCR register is:

  • A read/write register.
  • Accessed by a read or write at offset 0x4 of the DP address map when SELECT.DPBANKSEL is set to 0x1.

The following figure shows the Data Link Control Register bit assignments.

Figure A-11 Data Link Control Register bit assignments
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The following table shows the Data Link Control Register bit assignments.

Table A-19 Data Link Control Register bit assignments

Bits Function Description
[31:10] - Reserved, SBZ/RAZ.
[9:8] TURNROUND

Turnaround tristate period. This field only supports 0b00, other write values are treated as a protocol error.

The reset value is 0b00.

[7:6] WIREMODE

This field identifies SW-DP as operating in Synchronous mode only. It is fixed to 0b00.

The reset value is 0b00.

[5:3] - Reserved, SBZ/RAZ.
[2:0] PRESCALER Reserved, SBZ/RAZ.

Target Identification register, TARGETID (SW-DP only)

Target Identification register provides information about the target when the host is connected to a single device.

Attributes

The TARGETID register is:

  • A read-only register.
  • Accessed by a read at offset 0x4 of the DP register map when SELECT.DPBANKSEL is set to 0x2.

The following figure shows the Target Identification register bit assignments.

Figure A-12 Target Identification register bit assignments
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The following table shows the Target Identification register bit assignments.

Table A-20 Target Identification register bit assignments

Bits Function Description
[31:28] TREVISION Target revision.
[27:12] TPARTNO

Configuration dependent.

The designer of the part assigns this value and must be unique to that part.

[11:1] TDESIGNER Arm designer code (0x23B).
[0] - Reserved, RAO.

Data Link Protocol Identification Register, DLPIDR (SW-DP only)

Data Link Protocol Identification register provides protocol version information.

Attributes

The DLPIDR is:

  • A read-only register.
  • Accessed by a read at offset 0x4 of the DP register map when SELECT.DPBANKSEL is set to 0x3.

The following figure shows the Data Link Protocol Identification Register bit assignments.

Figure A-13 Data Link Protocol Identification Register bit assignments
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The following table shows the Data Link Protocol Identification Register bit assignments.

Table A-21 Data Link Protocol Identification Register bit assignments

Bits Function Description
[31:28] Target Instance

Configuration dependent.

This field defines a unique instance number for this device within the system. This value must be unique for all devices that are connected together in a multidrop system with identical values in the TREVISION fields in the TARGETID register. The value of this field reflects the value of the instanceid[3:0] input.

[27:4] - Reserved.
[3:0] Protocol Version

Defines the serial wire protocol version. This value is 0x1, that indicates SW protocol version 2.

Read Resend register, RESEND (SW-DP only)

Read Resend register enables the read data to be recovered from a corrupted debugger transfer without repeating the original AP transfer.

Attributes

The RESEND register is:

  • A read-only register.
  • Accessed by a read at offset 0x8 in the DP register map.

Performing a read to the RESEND register does not capture new data from the AP, it returns the value that was returned by the last AP read or DP RDBUFF read.

Reading the RESEND register enables the read data to be recovered from a corrupted SW-DP transfer without having to re-issue the original read request, or generate a new access to the connected debug memory system.

The RESEND register can be accessed multiple times, it always returns the same value until a new access is made to an AP register or the DP RDBUFF register.

DP register descriptions

More information about the DP registers, their features, and how to access them can be found in the

Arm® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2.

a Implemented on SW-DP only. On a JTAG-DP, this bit is Reserved, SBZ.
b In the Control/Status Register, see Control/Status register, CTRL/STAT.
c Field width, in bits, and the corresponding bits in the Identification Code Register.
d RO on SW-DP. On a JTAG-DP, this bit can be read normally. Writing a 1 to this bit sets the bit to 0.
e Implemented on SW-DP only. On a JTAG-DP, this bit is Reserved,RAZ.
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