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The FPU provided full-compliance, flush-to-zero, and Default NaN modes of operation.
In full-compliance mode, the FPU processes all operations according to the IEEE 754 standard in hardware.
Setting the FPSCR.FZ bit enables Flush-to-Zero (FZ) mode.
In FZ mode, the FPU treats all subnormal input operands of arithmetic
operations as zeros in the operation. Exceptions that result from a zero operand are
VMOV are not considered arithmetic
operations and are not affected by FZmode. A result that is tiny, as described in the IEEE 754 standard, where the destination precision is
smaller in magnitude than the minimum normal value before
rounding, is replaced with a zero. The FPSCR.IDC bit indicates when an input flush
occurs. The FPSCR.UFC bit indicates when a result flush occurs.
Setting the FPSCR.DN bit enables Default NaN (DN) mode.
In NaN mode, the result of any arithmetic data processing operation that
involves an input NaN, or that generates a NaN result, returns the default NaN. Propagation
of the fraction bits is maintained only by
VMOV operations. All
other arithmetic operations ignore any information in the fraction bits of an input NaN.