This appendix summarizes the behavior of the Cortex®‑M33 processor in cases where the Armv8‑M architecture is unpredictable.
C.1 Use of instructions defined in architecture variants.
C.2 Use of Program Counter - R15 encoding.
C.3 Use of Stack Pointer - as a general purpose register R13 .
C.4 Register list in load and store multiple instructions.
C.5 Exception-continuable instructions.
C.6 Stack limit checking.
C.7 UNPREDICTABLE instructions within an IT block.
C.8 Memory access and address space.
C.9 Load exclusive and Store exclusive accesses.
C.10 Armv8-M MPU programming.
C.11 Miscellaneous UNPREDICTABLE instruction behavior.