B6.1 About external coprocessors

The Cortex®‑M33 processor supports an external coprocessor interface which allows the integration of tightly coupled accelerator hardware with the processor. The programmers model allows software to communicate with the hardware using architectural coprocessor instructions.

The external coprocessor interface:

  • Supports up to eight separate coprocessors, CP0-CP7, depending on your implementation. The remaining coprocessor numbers, C8-C15, are reserved. CP10 and CP11 are always reserved for hardware floating-point. For more information, see the Armv8‑M Architecture Reference Manual.
  • Supports low-latency data transfer from the processor to and from the accelerator components.
  • Has a sustained bandwidth up to twice of the processor memory interface.
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