C.9 Load exclusive and Store exclusive accesses

Instructions which can generate an exclusive memory access such as LDREX and STREX have a number of restrictions and behavior defined as unpredictable in the Armv8‑M architecture.

In the Cortex®‑M33 processor:

  • Exclusive accesses to memory regions marked as Device outside of the PPB region behaves the same as an equivalent access to shared Normal memory. All Device memory is shared in Armv8‑M.
  • Exclusive accesses to the PPB memory region (0xE0000000:0xE00FFFFF) do not update the internal local exclusive monitor. Load exclusive instructions load data into a register and Store exclusive instructions store data from a register. For STREX and STLEX instructions, the status register is always updated with the value 0, indicating the store has updated memory.
  • The internal exclusive monitor does not tag addresses and the reservation granule is the whole of the memory. This means exclusive Load and Store instruction pairs that only use the local monitor are not affected by the address used for the access or the data size or the attributes associated with the memory regions. The behavior of unpredictable exclusive accesses to external memory depends on the global exclusive monitor in your system.
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