C.5 Exception-continuable instructions

To improve interrupt response and increase processing throughput, the processor can take an interrupt during the execution of a Load Multiple or Store Multiple instruction, and continue execution of the instruction after returning from the interrupt. During the interrupt processing, the EPSR.ICI bits hold the continuation state of the Load Multiple or Store Multiple instruction.

In the Cortex®‑M33 processor, any values of ICI bits that were not legally written, because of an interruption to an exception-continuable instruction, generate an INVSTATE UsageFault exception on attempt to re-execute the interrupted instruction. This includes the architecturally UNPREDICTABLE cases of:

  • Not a register in the register list of the Load Multiple or Store Multiple instruction.
  • The first register in the register list of the Load Multiple or Store Multiple instruction.

The Cortex‑M33 processor also generates an INVSTATE UsageFault exception if the ICI bits are set to any nonzero value for the following instructions, as these instructions are not eligible for continuation:

  • An integer Load Multiple instruction with the base register in the register list, and ICI set to a greater register number than the base register.
  • An integer Store Multiple instruction with base write-back and with the base register in the register list.

The INVSTATE UsageFault exception takes precedence over any other instruction-related fault type, including NOCP or UNDEFINSTR UsageFault.

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