A1.9 Product revisions

This section describes the differences in functionality between product revisions.

r0p0First release.
r0p1

The following changes that are made in this release:

  • Updated the CPUID reset value, 0x410FD211.
  • The Cortex®‑M33 processor optionally supports stalls to guarantee the delivery of trace packets. As a result, the ITM_TCR.STALLENA bit field is now RW.
  • Various engineering errata fixes.
r0p2

The following changes that are made in this release:

  • Updated the CPUID reset value, 0x410FD212 in this release.
  • Various engineering errata fixes.
r0p3

The following changes that are made in this release:

  • Updated the CPUID reset value, 0x410FD213 in this release.
  • Various engineering errata fixes.
r0p4

The following changes that are made in this release:

  • Updated the CPUID reset value, 0x410FD214 in this release.
  • Various engineering errata fixes.
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