D.1 Revisions

The tables that follow show the technical changes between released issues of this book.

Table D-1 Issue 0000-00

Change Location Affected
First release - -

Table D-2 Differences between issue 0000-00 and issue 0001-00

Change Location Affected
Updated CPUID reset value

B2.1 Identification register summaryB2.3 CPUID Base Register

r0p1
Revised the functional block diagram and associated note A1.4 Component blocks All
Revised the memory model description B1.4 Memory model All
Revised the exception handling and prioritization in Secure and Non-secure state description B1.7.1 Exception handling and prioritization All
Removed a redundant sentence 'Registers not described here are described in the Arm®v8-M Architecture Reference Manual' B4.1 NVIC programmers model All
Revised the usage restrictions description Chapter B6 External coprocessors All
Removed footnote in the ITM register summary table C2.1.1 ITM register summary table r0p1
Clarified that the functionality of the INT_ATVALID and INT_ATREADY Registers is only present in integration mode C2.1.5 Integration Mode Read ATB Ready RegisterC2.1.4 Integration Mode Write ATB Valid Register All

Table D-3 Differences between issue 0001-00 and issue 0002-00

Change Location Affected
Updated CPUID reset value B2.1 Identification register summaryB2.3 CPUID Base Register r0p2
Updated AHB-AP Identification value AHB-AP Identification Register, IDR, 0xFC r0p2

Table D-4 Differences between issue 0002-00 and issue 0003-00

Change Location Affected
Updated CPUID reset value. B2.1 Identification register summaryB2.3 CPUID Base Register r0p3
In the third paragraph, changed 'associated external memory access is marked as Non-secure' to 'associated memory access is marked as Non-secure'. Clarified use of the register SAU_CTRL.EN and SAU_CTRL.ALLNS bit fields. B3.1 About security attribution and memory protection/> All
Corrected the regions that show in the example of highest security level region Table   B3-1 Examples of Highest Security Level Region All
Corrected the NVIC short description register names B4.1.1 NVIC register summary All
Corrected the FPU exception flags names B5.2.4 Exceptions All
In the note, changed CPACR[2n+1:2n] to CPACR[2n+1:2n] B6.5 Configuring which coprocessors are included in Secure and Non-secure states All
Corrected the ROM table value for when the ETM is not implemented. Changed 0xFFF42003 to 0xFFF42002 C1.1.3 Processor ROM table identification and entries All

Table D-5 Differences between issue 0003-00 and issue 0004-00

Change Location Affects
Updated CPUID reset value

Table   B2-1 Identification register summary

B2.3 CPUID Base Register

r0p4
Corrected the INVSTATE UsageFault exception statement at the end of the Exception-continuable instruction description C.5 Exception-continuable instructions All
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