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The processor has various external interfaces.
Harvard AHB bus architecture supporting exclusive transactions and security state.
The External PPB (EPPB) APB interface enables access to CoreSight-compatible debug and trace components in a system connected to the processor.
The processor has an interface that connects to an external Implementation Defined Attribution Unit (IDAU), which enables your system to set security attributes based on address.
The ATB interfaces output trace data for debugging. The ATB interfaces are compatible with the CoreSight architecture. See the Arm® CoreSight™ Architecture Specification v2.0 for more information. The instruction ATB interface is used by the optional ETM, and the instrumentation ATB interface is used by the optional Instrumentation Trace Macrocell (ITM).
The Micro Trace Buffer (MTB) AHB slave interface and SRAM interface are for the optional CoreSight Micro Trace Buffer.
The coprocessor interface is designed for closely coupled external accelerator hardware.
The Debug AHB (D-AHB) slave interface allows a debugger access to registers, memory, and peripherals. The D-AHB interface provides debug access to the processor and the complete memory map.
The processor includes an optional Cross Trigger Interface (CTI) Unit that has an interface that is suitable for connection to external CoreSight components using a Cross Trigger Matrix (CTM).
The processor optionally supports a number of internal power domains which can be enabled and disabled using Q-channel interfaces connected to a Power Management Unit (PMU) in the system.