A1.6 Compliance

The processor complies with, or implements, the relevant Arm® architectural standards and protocols, and relevant external standards.

This book complements architecture reference manuals, architecture specifications, protocol specifications, and relevant external standards. It does not duplicate information from these sources.

Arm® architecture

The processor is compliant with the following:

  • Armv8‑M Main Extension.
  • Armv8‑M Security Extension.
  • Armv8‑M Protected Memory System Architecture (PMSA).
  • Armv8‑M Floating-point Extension.
  • Armv8‑M Digital Signal Processing (DSP) Extension.
  • Armv8‑M Debug Extension.
  • Armv8‑M Flash Patch Breakpoint (FPB) architecture version 2.0.

Bus architecture

The processor provides external interfaces that comply with the AMBA 5 AHB5 protocol. The processor also implements interfaces for CoreSight and other debug components using the APB4 protocol and ATBv1.1 part of the AMBA 4 ATB protocol.

For more information, see the:

  • Arm® AMBA® 5 AHB Protocol Specification.
  • AMBA® APB Protocol Version 2.0 Specification.
  • Arm® AMBA® 4 ATB Protocol Specification ATBv1.0 and ATBv1.1.

The processor also provides a Q-Channel interface. See the AMBA® Low Power Interface Specification Arm® Q-Channel and P-Channel Interfaces


The debug features of the processor implement the Arm debug interface architecture.

See the Arm® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2

Embedded Trace Macrocell

The trace features of the processor implement the Arm Embedded Trace Macrocell (ETM) v4.2 architecture.

See the Arm® CoreSight™ ETM‑M33 Technical Reference Manual for more information.

Floating-Point Unit

The Cortex®‑M33 processor with FPU supports single-precision arithmetic as defined by the FPv5 architecture that is part of the Armv8‑M architecture. The FPU provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic.

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