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The MTB provides a simple low-cost execution trace solution for the Cortex®‑M33 processor.
Trace is written to an SRAM interface, and can be extracted using a dedicated AHB slave interface (M-AHB) on the processor. The MTB can be controlled by memory mapped registers in the PPB region or by events generated by the DWT or through the CTI.
See the Arm® CoreSight™ MTB-M33 Technical Reference Manual for more information.